User manual

ManualsBrandsRenesas ManualsOtherAnswering Machine g1a

User’s Manual

RL78/G1

User’s Manual: Hardware

16-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

Rev.2.00 Jul 2013

Summary of content (1004 pages)

PAGE 1
User’s Manual 16 RL78/G1A User’s Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.
PAGE 2
Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.
PAGE 3
NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
PAGE 4
How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the RL78/G1A and design and develop application systems and programs for these devices. The target products are as follows. Purpose • 25-pin: R5F10E8x (x = A, C, D, E) • 32-pin: R5F10EBx (x = A, C, D, E) • 48-pin: R5F10EGx (x = A, C, D, E) • 64-pin: R5F10ELx (x = C, D, E) This manual is intended to give users an understanding of the functions described in the Organization below.
PAGE 5
Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...×××× or ××××B Numerical representations: Binary ...×××× Decimal Hexadecimal Related Documents ...××××H The related documents indicated in this publication may include preliminary versions.
PAGE 6
Other Documents Document Name Renesas MPUs & MCUs RL78 Family Document No. R01CP0003E Semiconductor Package Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Semiconductor Reliability Handbook R51ZZ0001E Note See the “Semiconductor Package Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp).
PAGE 7
CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 1.2 1.3 1.4 1.5 1.6 Features ....................................................................................................................................... 1 List of Part Numbers ................................................................................................................... 4 Pin Configuration (Top View)..............
PAGE 8
3.3 3.4 Instruction Address Addressing ............................................................................................. 79 3.3.1 Relative addressing ...................................................................................................................... 79 3.3.2 Immediate addressing................................................................................................................... 79 3.3.3 Table indirect addressing.............................................
PAGE 9
4.5 4.6 4.4.4 Handling different potential (1.8 V or 2.5 V) by using EVDD ≤ VDD ............................................... 116 4.4.5 Handling different potential (1.8 V or 2.5 V) by using I/O buffers ................................................ 116 Register Settings When Using Alternate Function.............................................................. 118 4.5.1 Basic concept when using alternate function ..............................................................................
PAGE 10
6.3 6.2.1 Timer count register mn (TCRmn) .............................................................................................. 193 6.2.2 Timer data register mn (TDRmn) ................................................................................................ 195 Registers Controlling Timer Array Unit ................................................................................ 196 6.3.1 Peripheral enable register 0 (PER0) .............................................................
PAGE 11
6.10.1 Cautions when using timer output............................................................................................... 291 CHAPTER 7 REAL-TIME CLOCK........................................................................................................ 292 7.1 7.2 7.3 Functions of Real-time Clock................................................................................................. 292 Configuration of Real-time Clock ..............................................................
PAGE 12
9.2 9.3 9.4 Configuration of Clock Output/Buzzer Output Controller................................................... 329 Registers Controlling Clock Output/Buzzer Output Controller .......................................... 329 9.3.1 Clock output select registers n (CKSn) ....................................................................................... 329 9.3.2 Registers controlling port functions of pins to be used for clock or buzzer output.......................
PAGE 13
11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) ..................................... 381 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode)..................................... 382 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ....................................... 383 11.7 A/D Converter Setup Flowchart ............................................................................................. 384 11.7.
PAGE 14
12.5.2 Master reception ......................................................................................................................... 447 12.5.3 Master transmission/reception .................................................................................................... 457 12.5.4 Slave transmission...................................................................................................................... 467 12.5.5 Slave reception ...............................................
PAGE 15
13.5.3 Transfer direction specification ................................................................................................... 591 13.5.4 Acknowledge (ACK).................................................................................................................... 592 13.5.5 Stop condition ............................................................................................................................. 593 13.5.6 Wait .........................................................
PAGE 16
15.5.1 CSI consecutive transmission..................................................................................................... 677 15.5.2 Consecutive capturing of A/D conversion results........................................................................ 679 15.5.3 UART consecutive reception + ACK transmission ...................................................................... 681 15.5.4 Holding DMA transfer pending by DWAITn bit...........................................................
PAGE 17
CHAPTER 19 RESET FUNCTION........................................................................................................ 740 19.1 Timing of Reset Operation ..................................................................................................... 742 19.2 States of Operation During Reset Periods ........................................................................... 744 19.3 Register for Confirming Reset Source..........................................................................
PAGE 18
24.3 Format of On-chip Debug Option Byte ................................................................................. 798 24.4 Setting of Option Byte ............................................................................................................ 799 CHAPTER 25 FLASH MEMORY .......................................................................................................... 800 25.1 Serial Programming Using Flash Memory Programmer .....................................................
PAGE 19
28.1 Conventions Used in Operation List ..................................................................................... 830 28.1.1 Operand identifiers and specification methods ........................................................................... 830 28.1.2 Description of operation column ................................................................................................. 831 28.1.3 Description of flag operation column.................................................................
PAGE 20
30.6.2 Temperature sensor, internal reference voltage output characteristics ...................................... 948 30.6.3 POR circuit characteristics.......................................................................................................... 948 30.6.4 LVD circuit characteristics........................................................................................................... 949 30.6.5 30.7 30.8 30.9 30.10 Supply voltage rise slope characteristics ...........................
PAGE 21
R01UH0305EJ0200 Rev.2.00 Jul 04, 2013 RL78/G1A RENESAS MCU CHAPTER 1 OUTLINE 1.1 Features Ultra-low power consumption technology • VDD = single power supply voltage of 1.6 to 3.6 V which can operate a 1.8 V device at a low voltage • HALT mode • STOP mode • SNOOZE mode RL78 CPU core • CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz operation with highspeed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.
PAGE 22
RL78/G1A CHAPTER 1 OUTLINE DMA (Direct Memory Access) controller • 2 channels • Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks Multiplier and divider/multiply-accumulator • 16 bits × 16 bits = 32 bits (Unsigned or signed) • 32 bits ÷ 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed) Serial interface • CSI: 2 to 6 channels • UART/UART (LIN-bus supported): 2 or 3 channels • I2C/Simplified I2C communication: 2 to 7 channels Timer • 16-
PAGE 23
RL78/G1A CHAPTER 1 OUTLINE { ROM, RAM capacities Flash ROM Data flash RAM 4 KB Note RL78/G1A 25 pins 32 pins 48 pins 64 pins R5F10E8E R5F10EBE R5F10EGE R5F10ELE 64 KB 4 KB 48 KB 4 KB 3 KB R5F10E8D R5F10EBD R5F10EGD R5F10ELD 32 KB 4 KB 2 KB R5F10E8C R5F10EBC R5F10EGC R5F10ELC 16 KB 4 KB 2 KB R5F10E8A R5F10EBA R5F10EGA − Note This is about 3 KB when the self-programming function and data flash function are used. (For details, see CHAPTER 3) R01UH0305EJ0200 Rev.2.
PAGE 24
RL78/G1A CHAPTER 1 OUTLINE 1.2 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/G1A Part No. R 5 F 1 0 E L C A x x x F B # V 0 Packing #U0 : Tray (HWQFN, VFBGA, WFLGA) #V0 : Tray (LFQFP) #W0 : Embossed Tape (HWQFN, VFBGA, WFLGA) #X0 : Embossed Tape (LFQFP) Package type: BG : VFBGA, 0.40 mm pitch FB : LFQFP, 0.50 mm pitch LA : WFLGA, 0.50 mm pitch NA : HWQFN, 0.
PAGE 25
RL78/G1A CHAPTER 1 OUTLINE Table 1-1. List of Ordering Part Numbers Pin count 25 pins Package 25-pin plastic WFLGA Note 1 Fields of Application A (3 × 3 mm, 0.
PAGE 26
RL78/G1A CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 25-pin products • 25-pin plastic WFLGA (3 × 3 mm, 0.
PAGE 27
RL78/G1A CHAPTER 1 OUTLINE 1.3.2 32-pin products AVSS AVDD P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5) • 32-pin plastic HWQFN (5 × 5 mm, 0.
PAGE 28
RL78/G1A CHAPTER 1 OUTLINE 1.3.3 48-pin products P140/PCLBUZ0/INTP6 P02/ANI17/TxD1/TI00/(KR0) P03/ANI16/RxD1/TO00/(KR1) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/(KR2) P23/ANI3/(KR3) P24/ANI4/(KR4) P25/ANI5/(KR5) P26/ANI6 P27/ANI7 • 48-pin plastic LFQFP (7 × 7 mm, 0.
PAGE 29
RL78/G1A CHAPTER 1 OUTLINE P140/PCLBUZ0/INTP6 P02/ANI17/TxD1/TI00/(KR0) P03/ANI16/RxD1/TO00/(KR1) P130 P20/ANI0/AVREFP P21/ANI1/AVREFM P22/ANI2/(KR2) P23/ANI3/(KR3) P24/ANI4/(KR4) P25/ANI5/(KR5) P26/ANI6 P27/ANI7 • 48-pin plastic HWQFN (7 × 7 mm, 0.
PAGE 30
RL78/G1A CHAPTER 1 OUTLINE 1.3.4 64-pin products AVSS AVDD P150/ANI8 P151/ANI9/(KR6) P152/ANI10/(KR7) P153/ANI11/(KR8) P154/ANI12/(KR9) P10/ANI18/SCK00/SCL00/(KR0) P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/(KR5) P16/TI01/TO01/INTP5 P51/ANI25/SO11/INTP2 P50/ANI26/SI11/SDA11/INTP1 • 64-pin plastic LFQFP (10 × 10 mm, 0.
PAGE 31
RL78/G1A CHAPTER 1 OUTLINE • 64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch) Top View Bottom View 8 7 6 5 4 3 2 1 A B C D E F G H H G F E D C B A Index mark Pin No. Name Pin No. Name Pin No. Name Pin No.
PAGE 32
RL78/G1A CHAPTER 1 OUTLINE 1.
PAGE 33
RL78/G1A CHAPTER 1 OUTLINE 1.5 Block Diagram 1.5.
PAGE 34
RL78/G1A CHAPTER 1 OUTLINE 1.5.
PAGE 35
RL78/G1A CHAPTER 1 OUTLINE 1.5.
PAGE 36
RL78/G1A CHAPTER 1 OUTLINE 1.5.
PAGE 37
RL78/G1A CHAPTER 1 OUTLINE 1.6 Outline of Functions (1/2) Item Code flash memory (KB) Data flash memory (KB) 25-pin 32-pin 48-pin 64-pin R5F10E8x R5F10EBx R5F10EGx R5F10ELx 16 to 64 16 to 64 16 to 64 32 to 64 4 4 Note1 RAM (KB) 2 to 4 2 to 4 4 Note1 2 to 4 4 Note1 2 to 4 Note1 Address space 1 MB Main system High-speed system clock clock X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.
PAGE 38
RL78/G1A CHAPTER 1 OUTLINE (2/2) Item 25-pin R5F10E8x 32-pin R5F10EBx 48-pin R5F10EGx 64-pin R5F10ELx 1 2 2 2 Clock output/buzzer output • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: fMAIN = 20 MHz operation) • 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz, 4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz (Subsystem clock: fSUB = 32.
PAGE 39
RL78/G1A CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Function Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is shown below. Table 2-1.
PAGE 40
RL78/G1A CHAPTER 2 PIN FUNCTIONS Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions. 2.1.
PAGE 41
RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Pin Type I/O After Reset P121 2-2-1 Input Input port P137 2-1-2 Input Input port RESET 2-1-1 Input − P122 Alternate Function X1 X2/EXCLK R01UH0305EJ0200 Rev.2.00 Jul 04, 2013 INTP0 Function Port 12. 2-bit input only port. Port 13. 1-bit input only port. − Input only pin for external reset When external reset is not used, connect this pin to VDD directly or via a resistor.
PAGE 42
RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.1.2 32-pin products (1/2) Function Name Pin Type P02 7-3-2 P03 8-3-2 I/O I/O After Reset Analog input port Alternate Function Function ANI17/TI00/TxD1/ (KR1) Port 0. ANI16/TO00/RxD1/ (KR2) Input/output can be specified in 1-bit units. 2-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P03 can be set to TTL input buffer.
PAGE 43
RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Pin Type Name P50 7-3-2 P51 I/O I/O 7-1-1 After Reset Analog input port Input port Alternate Function Function ANI26/INTP1/SI11/ SDA11 Port 5. INTP2/SO11 Input/output can be specified in 1-bit units. 2-bit I/O port. Use of an on-chip pull-up resistor can be specified by a software setting at input port. Output of P50 can be set to N-ch open-drain output (VDD tolerance).
PAGE 44
RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.1.3 48-pin products (1/2) Function Name Pin Type P02 7-3-2 P03 I/O I/O After Reset Analog input port 8-3-2 Alternate Function Function ANI17/TI00/TxD1/ Port 0. (KR0) 2-bit I/O port. ANI16TO00/RxD1/ Input/output can be specified in 1-bit units. (KR1) Use of an on-chip pull-up resistor can be specified by a software setting at input port. Input of P03 can be set to TTL input buffer.
PAGE 45
RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Name Pin Type P40 7-1-1 P41 7-3-1 I/O I/O After Reset Alternate Function Function Input port TOOL0 Port 4. Analog input port ANI30/TI07/TO07 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting at input port. P41 can be set to analog input P50 7-3-2 P51 7-3-1 I/O Analog input port Note 1 . ANI26/INTP1/SI11/ SDA11 Port 5.
PAGE 46
RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.1.4 64-pin products (1/3) Function Name Pin Type P00 8-1-1 I/O I/O After Reset Input port P01 Alternate Function TI00/(KR0) TO00/(KR1) P02 7-3-2 P03 8-3-2 P04 8-1-2 P05 7-1-1 Analog input port ANI17/SO10/TxD1/ (KR2) ANI16/SI10/RxD1/ SDA10/(KR3) Input port SCK10/SCL10/(KR4) TI05/TO05/KR8 P06 Function Port 0. 7-bit I/O port. Input/output can be specified in 1-bit units.
PAGE 47
RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/3) Function Pin Type Name P40 7-1-1 P41 P42 I/O After Reset Alternate Function Function Input port TOOL0 Port 4. 7-3-1 Analog input port ANI30/8TI07/TO07 4-bit I/O port. 7-1-1 Input port TI04/TO04 Input/output can be specified in 1-bit units. I/O − P43 Use of an on-chip pull-up resistor can be specified by a software setting at input port. P41 can be set to analog input P50 7-3-2 P51 7-3-1 I/O Analog input port Note .
PAGE 48
RL78/G1A CHAPTER 2 PIN FUNCTIONS (3/3) Function Pin Type Name P150 4-3-1 I/O I/O After Reset Analog input port Alternate Function Function ANI8 Port 15. P151 ANI9/(KR6) 5-bit I/O port. P152 ANI10/(KR7) P153 ANI11/(KR8) P154 ANI12/(KR9) RESET 2-1-1 Input − − Input/output can be specified in 1-bit units. Can be set to analog input Note . Input only pin for external reset When external reset is not used, connect this pin to VDD directly or via a resistor.
PAGE 49
RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.2 Functions Other than Port Pins 2.2.1 With functions for each product (1/4) Function Name R01UH0305EJ0200 Rev.2.
PAGE 50
RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/4) Function 64-pin 48-pin 32-pin 25-pin KR0 √ √ √ (√) KR1 √ √ (√) (√) KR2 √ √ (√) (√) KR3 √ √ (√) (√) KR4 √ √ (√) − KR5 √ √ (√) − KR6 √ − − − KR7 √ − − − KR8 √ − − − KR9 √ − − − PCLBUZ0 √ √ √ √ PCLBUZ1 √ √ √ − REGC √ √ √ √ RTC1HZ √ √ − − RESET √ √ √ √ RxD0 √ √ √ √ RxD1 √ √ √ √ RxD2 √ √ √ − SCK00 √ √ √ √ SCK01 √ √ − − SCK10 √ − − − SCK11 √ √ √ √ SCK20 √ √
PAGE 51
RL78/G1A CHAPTER 2 PIN FUNCTIONS (3/4) Function 64-pin 48-pin 32-pin 25-pin SI00 √ √ √ √ SI01 √ √ − − SI10 √ − − − SI11 √ √ √ √ SI20 √ √ √ − SI21 √ √ − − SO00 √ √ √ √ SO01 √ √ − − SO10 √ − − − SO11 √ √ √ √ SO20 √ √ √ − SO21 √ √ − − TI01 √ √ − − TI03 √ √ √ √ TI04 √ − − − TI05 √ − − − TI06 √ − − − TI07 √ √ − − TO00 √ √ √ √ TO01 √ √ − − TO03 √ √ √ √ TO04 √ − − − TO05 √ − − − TO06 √ − −
PAGE 52
RL78/G1A CHAPTER 2 PIN FUNCTIONS (4/4) Function 64-pin 48-pin 32-pin 25-pin VDD √ √ √ √ EVDD0 √ − − − AVDD √ √ √ √ AVREFP √ √ √ √ AVREFM √ √ √ √ VSS √ √ √ √ EVSS0 √ − − − Name R01UH0305EJ0200 Rev.2.
PAGE 53
RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.2.
PAGE 54
RL78/G1A CHAPTER 2 PIN FUNCTIONS (2/2) Function Name I/O − VDD Function <25-pin, 32-pin 48-pin> Positive power supply for port pin other than P20 to P27, P150 and RESET, REGC pin. <64-pin > Positive power supply for P121 to P124, P137 and RESET, REGC pin.
PAGE 55
RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-3 shows the connections of unused pins. Remark The pins mounted depend on the product. See 1.3 Pin Configuration (Top View) and 2.1 Port Function. Table 2-3. Connection of Unused Pins Pin Name P00 to P06 I/O Recommended Connection of Unused Pins Input: I/O Independently connect to EVDD0 or EVSS0 via a resistor. P10 to P16 Output: Leave open.
PAGE 56
RL78/G1A CHAPTER 2 PIN FUNCTIONS 2.4 Block Diagrams of Pins Figures 2-1 to 2-13 show the block diagrams of the pins described in 2.1.1 25-pin products to 2.1.4 64-pin products. Figure 2-1. Pin Block Diagram for Pin Type 1-1-1 Internal bus RD EVDD WRPORT P-ch Output latch Pmn (Pmn) N-ch EVSS Figure 2-2. Pin Block Diagram for Pin Type 2-1-1 RESET RESET Figure 2-3.
PAGE 57
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-4. Pin Block Diagram for Pin Type 2-2-1 Clock generator CMC OSCSEL/ OSCSELS RD Alternate function Internal bus P122/X2/EXCLK/Alternate function P124/XT2/EXCLKS/Alternate function CMC EXCLK, OSCSEL/ EXCLKS, OSCSELS N-ch P-ch RD Alternate function P121/X1/Alternate function P123/XT1/Alternate function Remark For alternate functions, see 2.1 Port Function. R01UH0305EJ0200 Rev.2.
PAGE 58
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-5. Pin Block Diagram for Pin Type 4-3-1 WRADPC 0: Analog input 1: Digital I/O ADPC ADPC3 to ADPC0 RD Internal bus 1 0 WRPORT VDD Output latch (Pmn) P-ch Pmn WRPM N-ch PM register (PMmn) VSS P-ch A/D converter N-ch R01UH0305EJ0200 Rev.2.
PAGE 59
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-6. Pin Block Diagram for Pin Type 7-1-1 EVDD WRPU PU register (PUmn) P-ch Alternate function Internal bus RD 1 0 WRPORT EVDD Output latch (Pmn) P-ch WRPM Pmn PM register (PMmn) N-ch EVSS Alternate function (SAU) Alternate function (other than SAU) Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0305EJ0200 Rev.2.
PAGE 60
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-7. Pin Block Diagram for Pin Type 7-1-2 EVDD WRPU PU register (PUmn) P-ch Alternate function RD Internal bus 1 0 WRPORT EVDD Output latch (Pmn) P-ch WRPM Pmn PM register (PMmn) N-ch WRPOM EVSS POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0305EJ0200 Rev.2.
PAGE 61
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-8. Pin Block Diagram for Pin Type 7-3-1 EVDD WRPU PU register (PUmn) P-ch WRPMC PMC register (PMCmn) Alternate function RD Internal bus 1 0 WRPORT EVDD Output latch (Pmn) P-ch Pmn WRPM N-ch PM register (PMmn) EVSS Alternate function (SAU) Alternate function (other than SAU) P-ch A/D converter N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0305EJ0200 Rev.2.
PAGE 62
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-9. Pin Block Diagram for Pin Type 7-3-2 WRPU EVDD PU register (PUmn) P-ch WRPMC PMC register (PMCmn) Alternate function RD Internal bus 1 0 WRPORT EVDD Output latch (Pmn) P-ch Pmn WRPM WRPOM N-ch PM register (PMmn) EVSS POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) P-ch A/D converter N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0305EJ0200 Rev.2.
PAGE 63
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-10. Pin Block Diagram for Pin Type 8-1-1 EVDD WRPU PU register (PUmn) P-ch WRPIM PIM register (PIMmn) Alternate function CMOS Internal bus RD 1 TTL 0 WRPORT EVDD Output latch (Pmn) P-ch WRPM Pmn PM register (PMmn) N-ch EVSS Alternate function (SAU) Alternate function (other than SAU) Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0305EJ0200 Rev.2.
PAGE 64
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-11. Pin Block Diagram for Pin Type 8-1-2 EVDD WRPU PU register (PUmn) P-ch WRPIM PMC register (PMCmn) Alternate function CMOS RD Internal bus 1 TTL 0 WRPORT EVDD Output latch (Pmn) P-ch WRPM Pmn PM register (PMmn) N-ch WRPOM EVSS POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0305EJ0200 Rev.2.
PAGE 65
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-12. Pin Block Diagram for Pin Type 8-3-2 WRPU EVDD PU register (PUmn) P-ch WRPIM PIM register (PMCmn) WRPMC Internal bus PMC register (PMCmn) Alternate function CMOS RD 1 TTL 0 WRPORT EVDD Output latch (Pmn) P-ch Pmn WRPM N-ch PM register (PMmn) WRPOM EVSS POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) P-ch A/D converter N-ch Remarks 1. 2. For alternate functions, see 2.1 Port Function.
PAGE 66
RL78/G1A CHAPTER 2 PIN FUNCTIONS Figure 2-13. Pin Block Diagram for Pin Type 12-1-1 Alternate function RD 1 0 Internal bus WRPORT Output latch (Pmn) Pmn N-ch WRPM PM register (PMmn) EVSS Alternate function (SAU) Alternate function (other than SAU) Remarks 1. 2. For alternate functions, see 2.1 Port Function. SAU: Serial array unit R01UH0305EJ0200 Rev.2.
PAGE 67
RL78/G1A CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the RL78/G1A can access a 1 MB address space. Figures 3-1 to 3-4 show the memory maps. R01UH0305EJ0200 Rev.2.
PAGE 68
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-1.
PAGE 69
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-2.
PAGE 70
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-3.
PAGE 71
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (R5F10ExE (x = 8, B, G, L)) 0FFFFH FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes Notes 1, 2 RAM 4 KB Program area FEF00H FEEFFH Mirror 51.
PAGE 72
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 0FFFFH Block 3FH 0FC00H 0FBFFH 007FFH 00400H 003FFH Block 01H Block 00H 1 KB 00000H (R5F10ExE (x = 8, B, G, L)) R01UH0305EJ0200 Rev.2.
PAGE 73
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1.
PAGE 74
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/G1A products incorporate internal ROM (flash memory), as shown below. Table 3-2.
PAGE 75
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-3.
PAGE 76
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-3.
PAGE 77
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The RL78/G1A mirrors the code flash area of 00000H to 0FFFFH, to F0000H to FFFFFH. The products with 96 KB or more flash memory mirror the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)).
PAGE 78
RL78/G1A CHAPTER 3 CPU ARCHITECTURE • Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 3-5.
PAGE 79
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.3 Internal data memory space The RL78/G1A products incorporate the following RAMs. Table 3-4.
PAGE 80
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FFF00H to FFFFFH (see Table 3-5 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.
PAGE 81
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G1A, based on operability and other considerations.
PAGE 82
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/G1A products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed.
PAGE 83
RL78/G1A CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PRn0L, PRn0H, PRn1L, PRn1H, PRn2L, PRn2H) (see 16.3.
PAGE 84
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
PAGE 85
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 3-11.
PAGE 86
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows.
PAGE 87
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5.
PAGE 88
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5.
PAGE 89
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5.
PAGE 90
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5.
PAGE 91
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-5.
PAGE 92
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
PAGE 93
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6.
PAGE 94
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6.
PAGE 95
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6.
PAGE 96
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6.
PAGE 97
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6.
PAGE 98
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Table 3-6.
PAGE 99
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: −128 to +127 or −32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination. Relative addressing is applied only to branch instructions.
PAGE 100
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT instructions.
PAGE 101
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR AX instructions. Figure 3-17.
PAGE 102
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Implied addressing can be applied only to MULU X. Figure 3-18. Outline of Implied Addressing Instruction code OP code A register Memory (register area) 3.4.
PAGE 103
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) ES:!addr16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) Figure 3-20.
PAGE 104
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH.
PAGE 105
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier SFR SFRP Description SFR name 16-bit-manipulatable SFR name (even address) Figure 3-23. Outline of SFR Addressing Instruction code FFFFFH OP code SFR FFF00H SFR Memory R01UH0305EJ0200 Rev.2.
PAGE 106
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description − [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) − ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register) Figure 3-24.
PAGE 107
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
PAGE 108
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-27. Example of [HL + byte], [DE + byte] [HL + byte], <1> [DE + byte] <2> <1> <2> FFFFFH Instruction code OP-code <2> <2> byte Offset <1> Address of an array rp(HL/DE) Either pair of registers <1> specifies the address where the target array of data starts in the 64 KB area from F0000H to FFFFFH. “byte” <2> specifies an offset within the array to the target location in memory.
PAGE 109
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-29. Example of word[BC] word [BC] <1> <2> FFFFFH Instruction code <2> <2> OP-code rp(BC) Low Addr. <1> High Addr. <1> Target memory Offset Address of a word within an array “word” <1> specifies the address where the target array of word-sized data starts in the 64 KB area from F0000H to FFFFFH. A pair of registers <2> specifies an offset within the array to the target location in memory. Array of word-sized data F0000H Memory Figure 3-30.
PAGE 110
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-31. Example of ES:word[B], ES:word[C] ES: word [B]㧘ES: word [C] <1> <2> <3> <1> <2> <3> Instruction code XFFFFH <3> <3> <2> Low Addr. Array of word-sized data Target memory Offset OP-code r(B/C) <2> Address of a word within an array High Addr. <1> ES X0000H X0000H Specifies a <1> 64 KB area The ES register <1> specifies a 64 KB area within the overall Memory 1-Mbyte space as the four higher-order bits, X, of the address range.
PAGE 111
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address.
PAGE 112
RL78/G1A CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Only the internal RAM area can be set as the stack area.
PAGE 113
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-36. Example of POP POP rp <1> <2> <1> Instruction code OP-code <2> SP SP SP+2 SP+1 SP (SP+1) (SP) Stack area F0000H rp Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively. The value of SP <3> is increased by two (if rp is the program status word (PSW), the content of address SP + 1 is stored in the PSW).
PAGE 114
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-38. Example of RET RET <1> <1> Instruction code SP OP-code SP SP+4 SP+3 SP+2 SP+1 <3> SP (SP+3) (SP+2) (SP+1) (SP) <2> PC Stack area F0000H Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>. The value of SP <3> is increased by four. Memory Figure 3-39.
PAGE 115
RL78/G1A CHAPTER 3 CPU ARCHITECTURE Figure 3-40. Example of RETI, RETB RETI㧘RETB PSW <1> Instruction code <1> SP OP-code SP PC SP+4 SP+3 SP+2 SP+1 <3> SP <2> Stack addressing is specified <1>. The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>. The value of SP <3> is increased by four. R01UH0305EJ0200 Rev.2.
PAGE 116
RL78/G1A CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The RL78/G1A microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. R01UH0305EJ0200 Rev.2.
PAGE 117
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-1.
PAGE 118
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
PAGE 119
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input and reference voltage input (+ side and − side). To use P20/ANI0 to P27/ANI7 as digital I/O pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC). Use these pins starting from the upper bit.
PAGE 120
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P41 to P43 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). The P41 pin can be specified as digital input/output or analog input, using port mode control register 4 (PMC4).
PAGE 121
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 7 Port 7 is an I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 7 (PU7). Output from the P71 and P74 pins can be specified as N-ch open-drain output (VDD toleranceNote 1/EVDD toleranceNote 2) in 1-bit units using port output mode register 7 (POM7).
PAGE 122
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.2.11 Port 14 Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140, P141 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). This port can also be used for clock/buzzer output, and external interrupt request input, Reset signal generation sets P140, P141 to input mode. 4.
PAGE 123
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers.
PAGE 124
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-4.
PAGE 125
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Register Settings When Using Alternate Function. Figure 4-1.
PAGE 126
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is readNote. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
PAGE 127
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to both normal output mode (POMmn = 0) and input mode (PMmn = 1) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
PAGE 128
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.4 Port input mode registers (PIMxx) These registers set the input buffer in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-4.
PAGE 129
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.5 Port output mode registers (POMxx) These registers set the output mode in 1-bit units. N-ch open drain output (VDD toleranceNote 1/EVDD toleranceNote 2) mode can be selected during serial communication with an external device of the different potential, and for the SDA00, SDA01, SDA10, SDA11, SDA20, and SDA21 pins during 2 simplified I C communication with an external device of the same potential.
PAGE 130
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.6 Port mode control registers (PMCxx) These registers set the digital I/O/analog input in 1-bit units. Port mode control registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. Figure 4-6.
PAGE 131
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.7 A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7, and P150/ANI8 to P154/ANI12 pins to digital I/O of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 4-7.
PAGE 132
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.8 Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. Use the PIOR register to assign a port to the function to redirect and enable the function. In addition, can be changed the settings for redirection until its function enable operation.
PAGE 133
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.9 Global digital input disable register (GDIDIS) This register is used to prevent through-current flowing to the input buffers of input ports which use EVDD0 as the power supply when the EVDD0 power supply is turned off. When not all of the I/O ports using EVDD0 as the power supply are used, low power consumption can be achieved by setting the GDIDIS register (to 1) to turn off the EVDD0 power supply.
PAGE 134
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.3.10 Global analog input disable register (GAIDIS) This register is used to prevent through-current flowing from the input buffers of input ports which use AVDD as the power supply when the AVDD power supply is turned off. When not all of the I/O ports using AVDD as the power supply are used, low power consumption can be achieved by setting the GAIDIS register (to 1) to turn off the AVDD power supply.
PAGE 135
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated.
PAGE 136
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.4.4 Handling different potential (1.8 V or 2.5 V) by using EVDD ≤ VDD When connecting an external device operating on a different potential (1.8 V or 2.5 V), it is possible to connect the I/O pins of general ports by changing EVDD0 to accord with the power supply of the connected device. 4.4.5 Handling different potential (1.8 V or 2.5 V) by using I/O buffers It is possible to connect an external device operating on a different potential (1.8 V or 2.
PAGE 137
RL78/G1A CHAPTER 4 PORT FUNCTIONS (2) Setting procedure when using output ports of UART0 to UART2, CSI00, CSI10, and CSI20 functions in N-ch open-drain output mode In case of UART0: P12 In case of UART1: P02 In case of UART2: P13 In case of CSI00: P10, P12 In case of CSI10: P02, P04 In case of CSI20: P13, P15 <1> Using an external resistor, pull up externally the output pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used).
PAGE 138
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.5 Register Settings When Using Alternate Function 4.5.1 Basic concept when using alternate function In the beginning, for a pin also assigned to be used for analog input, use the ADPC register or port mode control register (PMCxx) to specify whether to use the pin for analog input or digital input/output. Figure 4-11 shows the basic configuration of an output circuit for pins used for digital input/output.
PAGE 139
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-5.
PAGE 140
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.5.3 Register setting examples for used port and alternate functions Register setting examples for used port and alternate functions are shown in Table 4-6. The registers used to control the port functions should be set as shown in Table 4-6. See the following remark for legends used in Table 4-6.
PAGE 141
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 142
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 143
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 144
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 145
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 146
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 147
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 148
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 149
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 150
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 151
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 152
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 153
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 154
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 155
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 156
RL78/G1A CHAPTER 4 PORT FUNCTIONS Table 4-6.
PAGE 157
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.6 Cautions When Using Port Function 4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
PAGE 158
RL78/G1A CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings For an output pin to which multiple functions are assigned, the output of the unused alternate functions must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR). For details about the alternate function output, see 4.5 Register Settings When Using Alternate Function.
PAGE 159
RL78/G1A CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR The presence or absence of connecting resonator pin for main system clock, connecting resonator pin for subsystem clock, external clock input pin for main system clock, and external clock input pin for subsystem clock, depends on the product. Output pin 25, 32-pin 48, 64-pin X1, X2 pins √ √ EXCLK pin √ √ XT1, XT2 pins − √ EXCLKS pin − √ 5.
PAGE 160
RL78/G1A CHAPTER 5 CLOCK GENERATOR (2) Subsystem clock • XT1 clock oscillator This circuit oscillates a clock of fXT = 32.768 kHz by connecting a 32.768 kHz resonator to XT1 and XT2. Oscillation can be stopped by setting the XTSTOP bit (bit 6 of the clock operation status control register (CSC)). An external subsystem clock (fEXS = 32.768 KHz) can also be supplied from the EXCLKS/XT2/P124 pin. An external subsystem clock input can be disabled by the setting of the XTSTOP bit.
PAGE 161
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1.
PAGE 162
R01UH0305EJ0200 Rev.2.00 Jul 04, 2013 External input clock Crystal/ceramic oscillation IOscillation (3 MHz (TYP.)) IOscillation (4 MHz (TYP.)) fEXS fXT High-speed on-chip oscillator frequency select register (HOCODIV) STOP mode signal Clock operation status control register (CSC) XTSTOP HIOSTOP CLS Oscillation (15 kHz (TYP.)) Low-speed on-chip oscillator fIL HOCODIV2 HOCODIV1 HOCODIV0 fSUB IOscillation (2 MHz (TYP.)) fIH MSTOP (Remark is listed on the next page after next.
PAGE 163
RL78/G1A Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency fXT: XT1 clock oscillation frequency fEXS: External subsystem clock frequency fSUB: Subsystem clock frequency fCLK: CPU/peripheral hardware clock frequency fIL: Low-speed on-chip oscillator clock frequency 5.
PAGE 164
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-2.
PAGE 165
RL78/G1A CHAPTER 5 CLOCK GENERATOR Cautions 7. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. • Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems.
PAGE 166
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-3.
PAGE 167
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to C0H. Figure 5-4.
PAGE 168
RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-2. Stopping Clock Method Clock X1 clock External main system clock XT1 clock External subsystem clock High-speed on-chip oscillator clock Condition Before Stopping Clock (Invalidating External Clock Input) CPU and peripheral hardware clocks operate with a clock other than the high-speed system clock. Setting of CSC Register Flags MSTOP = 1 (CLS = 0 and MCS = 0, or CLS = 1) CPU and peripheral hardware clocks operate with a clock other than the subsystem clock.
PAGE 169
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H Symbol OSTC After reset: 00H 7 6 5 R 4 3 2 1 0 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 8 25.6 μs max. 12.8 μs max. 8 25.6 μs min. 0 0 0 0 0 0 0 0 2 /fX max. 1 0 0 0 0 0 0 0 2 /fX min. 12.
PAGE 170
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. When the X1 clock is made to oscillate by clearing the MSTOP bit to start the X1 oscillation circuit operating, actual operation is automatically delayed for the time set in the OSTS register.
PAGE 171
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 0 0 2 /fX 25.6 μs 12.8 μs 0 0 1 2 /fX 9 51.2 μs 25.6 μs 0 1 0 2 /fX 10 102 μs 51.
PAGE 172
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable register 0 (PER0) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each function before specifying the initial settings of the peripheral functions.
PAGE 173
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/3) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 RTCEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN ADCEN Control of A/D converter input clock supply Stops input clock supply. 0 • SFR used by the A/D converter cannot be written. • The A/D converter is in the reset status. Enables input clock supply. 1 • SFR used by the A/D converter can be read and written.
PAGE 174
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (3/3) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 RTCEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN SAU0EN Control of serial array unit 0 input clock supply Stops input clock supply. 0 • SFR used by the serial array unit 0 cannot be written. • The serial array unit 0 is in the reset status. Enables input clock supply.
PAGE 175
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.7 Subsystem clock supply mode control register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock and 12-bit interval timer, is stopped in STOP mode or HALT mode while subsystem clock is selected as CPU clock.
PAGE 176
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H). The HOCODIV register can be set by an 8-bit memory manipulation instruction.
PAGE 177
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted. The HIOTRM register can be set by an 8-bit memory manipulation instruction.
PAGE 178
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows.
PAGE 179
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-12. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock VSS XT1 32.768 kHz XT2 External clock EXCLKS Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-11 and 5-12 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines.
PAGE 180
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-13 shows examples of incorrect resonator connection. Figure 5-13. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 NG NG NG (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
PAGE 181
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-13. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 B X2 C High current (g) Signals are fetched VSS Caution X1 X2 When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning.
PAGE 182
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/G1A. The frequency can be selected from among 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset release. 5.4.
PAGE 183
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1).
PAGE 184
RL78/G1A CHAPTER 5 CLOCK GENERATOR Figure 5-14.
PAGE 185
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 6, 4, 3, 2, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H).
PAGE 186
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock.
PAGE 187
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock.
PAGE 188
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.4 CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15.
PAGE 189
RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A) Status Transition (A) → (B) SFR Register Setting SFR registers do not have to be set (default status after reset release).
PAGE 190
RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3.
PAGE 191
RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3.
PAGE 192
RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3.
PAGE 193
RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-3.
PAGE 194
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4.
PAGE 195
RL78/G1A CHAPTER 5 CLOCK GENERATOR Table 5-5.
PAGE 196
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.6 Time required for switchover of CPU clock and system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the highspeed on-chip oscillator clock and the high-speed system clock).
PAGE 197
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-7.
PAGE 198
RL78/G1A CHAPTER 5 CLOCK GENERATOR 5.7 Resonator and Oscillator Constants The resonators for which the operation is verified and their oscillator constants are shown below. Cautions 1. The oscillator constants shown above are reference values based on evaluation in a specific environment by the resonator manufacturer. Be sure to apply to the resonator manufacturer for evaluation on the actual circuit before using these constants for your application.
PAGE 199
RL78/G1A CHAPTER 5 CLOCK GENERATOR (1) X1 oscillation: Manufacturer Resonator As of February, 2013 (1/3) Note 1 Part Number SMD/ Frequency Flash Lead (MHz) operation Recommended Circuit Note 3 Constants (reference) Oscillation Voltage Range (V) Note 2 mode Murata Ceramic CSTCC2M00G56-R0 SMD 2.0 Manufacturing resonator CSTCR4M00G55-R0 SMD 4.0 CSTLS4M00G53-B0 Lead CSTCC2M00G56-R0 SMD 2.0 CSTCR4M00G55-R0 SMD 4.
PAGE 200
RL78/G1A CHAPTER 5 CLOCK GENERATOR (1) X1 oscillation: Manufacturer Resonator As of February, 2013 (2/3) Note 1 Part Number SMD/ Frequency Flash Lead (MHz) operation mode Recommended Circuit Note 3 Constants (reference) C1 (pF) C2 (pF) Rd (kΩ) MIN. MAX. (47) (47) 0 2.4 3.6 (39) 0 2.7 3.6 Ceramic CSTCC2M00G56-R0 SMD 2.0 Manufacturing resonator CSTCR4M00G55-R0 SMD 4.0 (39) CSTLS4M00G53-B0 Lead (15) (15) 0 CSTCR4M19G55-R0 SMD 4.
PAGE 201
RL78/G1A CHAPTER 5 CLOCK GENERATOR (1) X1 oscillation: Manufacturer As of February, 2013 (3/3) Resonator Part Number SMD/ Frequency Flash Recommended Circuit Oscillation Voltage Lead (MHz) operation Constants (reference) Range (V) Note 1 mode KYOCERA Note 2 Corporation Nihon Dempa Kogyo Note 3 Ceramic PBRV4.00MR50Y000 resonator PBRV4.00MR50Y000 Crystal Rd (kΩ) MIN. MAX. SMD 4.0 LV 15 15 0 1.6 3.6 SMD 4.0 LS 15 15 0 1.8 3.6 PRQV8.00CR5010Y000 SMD 8.
PAGE 202
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The timer array unit is provided in all products (Unit 0, Channels 0 to 7). Units Channels 25, 32, 48, 64-pin Unit 0 Channel 0 √ Channel 1 √ Channel 2 √ Channel 3 √ Channel 4 √ Channel 5 √ Channel 6 √ Channel 7 √ Cautions 1. The presence or absence of timer I/O pins depends on the product. See Table 6-2 Timer I/O Pins provided in Each Product for details. 2.
PAGE 203
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer. TIMER ARRAY UNIT channel 0 16-bit timers channel 1 channel 2 channel 6 channel 7 For details about each function, see the table below. Independent channel operation function Simultaneous channel operation function • Interval timer (→ see 6.8.
PAGE 204
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels. (1) Interval timer Each timer of a unit can be used as a reference timer that generates an interrupt (INTTMmn) at fixed intervals.
PAGE 205
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
PAGE 206
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated.
PAGE 207
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.1.4 LIN-bus supporting function (channel 7 of unit 0 only) Timer array unit is used to check whether signals received in LIN-bus communication match the LIN-bus communication format. (1) Detection of wakeup signal The timer starts counting at the falling edge of a signal input to the serial data input pin (RxD2) of UART2 and the count value of the timer is captured at the rising edge. In this way, a low-level width can be measured.
PAGE 208
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1.
PAGE 209
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT The presence or absence of timer I/O pins in each timer array unit channel depends on the product. Table 6-2. Timer I/O Pins provided in Each Product Timer array unit I/O Pins of Each Product channels 64-pin 48-pin Channel 0 25-pin TI00, TO00 Channel 1 Unit 0 32-pin − TI01/TO01 Channel 2 − Channel 3 TI03/TO03 Channel 4 TI04/TO04 − Channel 5 TI05/TO05 − Channel 6 TI06/TO06 − Channel 7 TI07/TO07 − Remarks 1.
PAGE 210
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-1.
PAGE 211
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-2.
PAGE 212
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-4.
PAGE 213
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.2.1 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn) (see 6.3.3 Timer mode register mn (TMRmn)). Figure 6-6.
PAGE 214
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT The TCRmn register read value differs as follows according to operation mode changes and the operating status. Table 6-3.
PAGE 215
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn). The value of the TDRmn register can be changed at any time. This register can be read or written in 16-bit units.
PAGE 216
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers.
PAGE 217
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
PAGE 218
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1, CKm2, CKm3) that are commonly supplied to each channel. CKm0 is selected by using bits 3 to 0 of the TPSm register, and CKm1 is selected by using bits 7 to 4 of the TPSm register. In addition, only for channel 1 and 3, CKm2 and CKm3 can be also selected.
PAGE 219
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-10. Format of Timer Clock Select register m (TPSm) (1/2) Address: F01B6H, F01B7H (TPS0) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPSm 0 0 PRS PRS 0 0 PRS PRS PRS PRS PRS PRS PRS PRS PRS PRS m31 m30 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 PRS PRS PRS mk3 mk2 mk1 mk0 0 0 0 0 fCLK 2 MHz 5 MHz 10 MHz 20 MHz 32 MHz 0 0 0 1 fCLK/2 1 MHz 2.
PAGE 220
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-10.
PAGE 221
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (fMCK), select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
PAGE 222
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11.
PAGE 223
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11.
PAGE 224
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11.
PAGE 225
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-11.
PAGE 226
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B). See Table 6-5 for the operation of the OVF bit in each operation mode and set/clear conditions. The TSRmn register can be read by a 16-bit memory manipulation instruction.
PAGE 227
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0.
PAGE 228
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1. The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 = 1), because they are trigger bits.
PAGE 229
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TEHm1, TEHm3 = 0), because they are trigger bits.
PAGE 230
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 5 of unit 0 timer input.. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-16.
PAGE 231
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output enable register m (TOEm) The TOEm register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TOmn bit of timer output register m (TOm) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TOmn).
PAGE 232
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output register m (TOm) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TOmn) of each channel. The TOmn bit oh this register can be rewritten by software only when timer output is disabled (TOEmn = 0). When timer output is enabled (TOEmn = 1), rewriting this register by software is ignored, and the value is changed only by the timer operation.
PAGE 233
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output level register m (TOLm) The TOLm register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In the master channel output mode (TOMmn = 0), this register setting is invalid.
PAGE 234
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output mode register m (TOMm) The TOMm register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
PAGE 235
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to implement LIN-bus communication operation by using channel 7 in association with the serial array unit. When the ISC1 bit is set to 1, the input signal of the serial data input pin (RxD2) is selected as a timer input signal. The ISC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-21.
PAGE 236
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise filter is enabled, after synchronization with the operating clock (fMCK) for the target channel, whether the signal keeps the same value for two clock cycles is detected.
PAGE 237
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-22.
PAGE 238
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.3.15 Registers controlling port functions of pins to be used for timer I/O Using port pins for the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target pins (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)). For details, see 4.3.1 Port mode registers (PMxx), 4.3.2 Port registers (Pxx), and 4.3.6 Port mode control registers (PMCxx).
PAGE 239
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply. (1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel. (2) Any channel, except channel 0, can be set as a slave channel.
PAGE 240
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Example TAU0 CKm0 Channel 0: Master Channel group 1 (Simultaneous channel operation function) Channel 1: Slave Channel 2: Slave Channel group 2 (Simultaneous channel operation function) Channel 3: independent channel operation function CKm1 CKm0 Channel 4: Master * The operating clock of channel group 1 may be different from that of channel group 2.
PAGE 241
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3, and there are several rules for using it. The basic rules for this function are as follows: (1) The 8-bit timer operation function applies only to channels 1 and 3.
PAGE 242
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (fTCLK) The count clock (fTCLK) of the timer array unit can be selected between following by CCSmn bit of timer mode register mn (TMRmn). . • Operation clock (fMCK) specified by the CKSmn0 and CKSmn1 bits • Valid edge of input signal input from the TImn pin Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK) are shown below.
PAGE 243
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (fTCLK) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input signal via the TImn pin (when a noise filter is used, the delay becomes 3 to 4 clock).
PAGE 244
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Operation of timer count register mn (TCRmn) is enabled by setting of TSmn bit of timer channel start register m (TSm). Operation from when counting is enabled to when timer count register mn (TCRmn) starts counting is shown in Table 6-6. Table 6-6.
PAGE 245
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation. <2> A start trigger is generated at the first count clock after operation is enabled. <3> When the MDmn0 bit is set to 1, INTTMmn is generated by the start trigger.
PAGE 246
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <3> As soon as 1 has been written to the TSmn bit and 1 has been set to the TEmn bit, the value of timer data register mn (TDRmn) is loaded to the TCRmn register to start counting.
PAGE 247
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation. <3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded to the TCRmn register and counting starts in the capture mode.
PAGE 248
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and count starts.
PAGE 249
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts.
PAGE 250
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TOmn Pin) Control 6.6.1 TOmn pin output circuit configuration Figure 6-30. Output Circuit Configuration <5> TOmn register Controller Interrupt signal of the master channel (INTTMmn) Interrupt signal of the slave channel (INTTMmp) Set TOmn pin Reset/toggle <1> <2> <3> <4> TOLmn TOMmn Internal bus TOEmn TOmn write signal The following describes the TOmn pin output circuit.
PAGE 251
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TOmn pin output setting The following figure shows the procedure and status transition of the TOmn output pin from initial setting to timer operation start. Figure 6-31.
PAGE 252
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6.
PAGE 253
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (2) Default level of TOmn pin and output level after timer operation start The change in the output level of the TOmn pin when timer output register m (TOm) is written while timer output is disabled (TOEmn = 0), the initial level is changed, and then timer output is enabled (TOEmn = 1) before port output is enabled, is shown below.
PAGE 254
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOMmp = 1) setting (PWM output)) When slave channel output mode (TOMmp = 1), the active level is determined by timer output level register m (TOLm) setting. Figure 6-33.
PAGE 255
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TOmn pin in slave channel output mode (TOMmn = 1) (a) When timer output level register m (TOLm) setting has been changed during timer operation When the TOLm register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output level of the TOmn pin.
PAGE 256
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-35.
PAGE 257
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TOmn bit In timer output register m (TOm), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TOmn bit of all the channels can be manipulated collectively. Only the desired bits can also be manipulated by enabling writing only to the TOmn bits (TOEmn = 0) that correspond to the relevant bits of the channel used to perform output (TOmn). Figure 6-36.
PAGE 258
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer (INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3 to 7) 6.6.
PAGE 259
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.7 Timer Input (TImn) Control 6.7.1 TImn pin input circuit configuration The signal input from a timer input pin passes through a noise filter and edge detector, and is then input to the timer controller. If it is necessary to eliminate noise at the pin in question, enable its noise filter. The configuration of the input circuit is shown below. Figure 6-39.
PAGE 260
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Cautions on channel input When timer input pins are not used, the operating clock is not supplied to the noise filters. When use of a timer input pin is specified, therefore, the system must wait for the time shown below until the channel operation enable trigger flag for the channel corresponding to the timer input pin is set.
PAGE 261
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8 Independent Channel Operation Function of Timer Array Unit 6.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals. The interrupt generation period can be calculated by the following expression.
PAGE 262
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Clock selection Figure 6-41. Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 CKm0 Trigger selection Operation clockNote TSmn Timer counter register mn (TCRmn) Output controller Timer data register mn(TDRmn) Interrupt controller TOmn pin Interrupt signal (INTTMmn) Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Figure 6-42.
PAGE 263
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-43.
PAGE 264
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode) 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode.
PAGE 265
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 266
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation TAU stop To hold the TOmn pin output level Clears the TOmn bit to 0 after the value to be held is set to the port register. When holding the TOmn pin output level is not necessary Setting not required. The TAUmEN bit of the PER0 register is cleared to 0. Hardware Status The TOmn pin output level is held by port function.
PAGE 267
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt. The specified number of counts can be calculated by the following expression.
PAGE 268
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn 3 TCRmn 0000H TDRmn 2 3 1 2 0 1 2 0 0003H 1 2 0 1 0002H INTTMmn 4 events Remarks 1. 4 events 3 events m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin (TOmn) : n = 0, 1, 3 to 7)) 2.
PAGE 269
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-47.
PAGE 270
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode.
PAGE 271
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 272
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as frequency divider (channel 0 of unit 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin. The divided clock frequency output from TO00 can be calculated by the following expression.
PAGE 273
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-50.
PAGE 274
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-51.
PAGE 275
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Operation Procedure When Frequency Divider Function Is Used Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0).
PAGE 276
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.4 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit is set to 1. The pulse interval can be calculated by the following expression.
PAGE 277
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-54. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH b a TCRmn d c 0000H TDRmn 0000H a b c d INTTMmn OVF Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin (TOmn) : n = 0, 1, 3 to 7)) 2.
PAGE 278
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 0 11 Note CKSmn1 CKSmn0 1/0 12 CCSmn M/S 0 0 0 10 9 8 7 6 5 4 0 0 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 1 1/0 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 0 1 0 1/0 Operation mode of channel n 010B: Capture mode Setting of operation when counting is started 0: Does not generate INTTMmn when counting is started.
PAGE 279
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 280
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.5 Operation as input signal high-/low-level width measurement Caution When using a channel to implement the LIN-bus, set bit 1 (ISC1) of the input switch control register (ISC) to 1. In the following descriptions, read TImn as RxD2. By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured.
PAGE 281
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-57. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement Clock selection CKm1 Operation clock Note CKm0 Timer counter register mn (TCRmn) TImn pin Noise filter Edge detection Trigger selection TNFENxx Timer data register mn (TDRmn) Interrupt controller Interrupt signal (INTTMmn) Note For channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3. Figure 6-58.
PAGE 282
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-59.
PAGE 283
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 284
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.8.6 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval. It is also possible to start counting down and generate INTTMmn (timer interrupt) at any interval by setting TSmn to 1 by software while TEmn = 1. The interrupt generation period can be calculated by the following expression.
PAGE 285
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn a b INTTMmn a+1 b+1 Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin (TOmn) : n = 0, 1, 3 to 7)) 2.
PAGE 286
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 1/0 1/0 12 11 Note CKSmn1 CKSmn0 CCSmn M/S 0 0 0/1 10 9 8 7 6 5 4 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 1 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1/0 0 0 1 0 0 0/1 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. 1: Trigger input is valid.
PAGE 287
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register m (TOLm) Bit n TOLm TOLmn 0: Cleared to 0 when TOMmn = 0 (master channel output mode). 0 (e) Timer output mode register m (TOMm) Bit n TOMm TOMmn 0: Sets master channel output mode. 0 Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7 (however, timer input pin (TImn), timer output pin (TOmn) : n = 0, 1, 3 to 7)) R01UH0305EJ0200 Rev.2.
PAGE 288
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 289
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.9 Simultaneous Channel Operation Function of Timer Array Unit 6.9.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin. The delay time and pulse width can be calculated by the following expressions.
PAGE 290
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-65.
PAGE 291
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-66. Example of Basic Timing of Operation as One-Shot Pulse Output Function (Start Trigger: TImn Pin Input Valid Edge.) TSmn TEmn TImn Master channel FFFFH TCRmn 0000H TDRmn a TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave channel 0000H TDRmp b TOmp INTTMmp a+2 b a+2 b Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p ≤ 7) However, timer output pin (TOmp) : p = 1, 3 to 7 2.
PAGE 292
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-67. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register mn (TMRmn) 15 TMRmn 14 13 CKSmn1 CKSmn0 1/0 0 12 CCSmn 0 0 11 10 9 8 7 6 5 4 MAS STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 TERmn 1 Note 0 0 1/0 1/0 3 2 1 0 MDmn3 MDmn2 MDmn1 MDmn0 1/0 0 0 1 0 0 0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid.
PAGE 293
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register mp (TMRmp) 15 TMRmp 14 13 0 11 Note CKSmp1 CKSmp0 1/0 12 CCSmp M/S 0 0 0 10 9 8 7 6 5 4 0 0 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 1 0 0 0 3 2 1 0 MDmp3 MDmp2 MDmp1 MDmp0 0 1 0 0 0 Operation mode of channel p 100B: One-count mode Start trigger during operation 0: Trigger input is invalid.
PAGE 294
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable registers 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 295
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Operation start Sets the TOEmp bit (slave) to 1 (only when operation is resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. The TSmn and TSmp bits automatically return to 0 because they are trigger bits. Count operation of the master channel is started by start trigger detection of the master channel.
PAGE 296
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.9.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions.
PAGE 297
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT CKm1 Operation clock CKm0 TSmn Trigger selection Master channel (interval timer mode) Clock selection Figure 6-70.
PAGE 298
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-71. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH Master channel TCRmn 0000H TDRmn a b TOmn INTTMmn TSmp TEmp FFFFH TCRmp Slave channel 0000H TDRmp c d TOmp INTTMmp a+1 c a+1 c b+1 d Remark 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p ≤ 7) However, timer output pin (TOmp) : p = 1, 3 to 7 2.
PAGE 299
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-72.
PAGE 300
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register mp (TMRmp) 15 TMRmp 14 13 0 11 Note CKSmp1 CKSmp0 1/0 12 CCSmp M/S 0 0 0 10 9 8 7 6 5 4 0 0 STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 1 0 0 0 3 2 1 0 MDmp3 MDmp2 MDmp1 MDmp0 0 1 0 0 1 Operation mode of channel p 100B: One-count mode Start trigger during operation 1: Trigger input is valid.
PAGE 301
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 302
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Operation Procedure When PWM Function Is Used (2/2) Software Operation Operation Sets the TOEmp bit (slave) to 1 (only when operation is start resumed). Hardware Status The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. TEmn = 1, TEmp = 1 When the master channel starts counting, INTTMmn is The TSmn and TSmp bits automatically return to 0 generated.
PAGE 303
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.9.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
PAGE 304
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT CKm1 Operation clock CKm0 TSmn Trigger selection Master channel (interval timer mode) Clock selection Figure 6-75.
PAGE 305
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-76. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) TSmn TEmn FFFFH Master channel TCRmn 0000H TDRmn a b TOmn INTTMmn TSmp TEmp FFFFH Slave channel 1 TCRmp 0000H TDRmp c d TOmp INTTMmp a+1 a+1 c c b+1 d d TSmq TEmq FFFFH Slave channel 2 TCRmq 0000H TDRmq e f TOmq INTTMmq a+1 e a+1 e b+1 f f (Remark is listed on the next page.) R01UH0305EJ0200 Rev.2.
PAGE 306
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n
PAGE 307
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-77.
PAGE 308
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-78.
PAGE 309
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register m (TPSm).
PAGE 310
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-79. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Operation (Sets the TOEmp and TOEmq (slave) bits to 1 only when resuming operation.) start The TSmn bit (master), and TSmp and TSmq (slave) bits of timer channel start register m (TSm) are set to 1 at the same time. The TSmn, TSmp, and TSmq bits automatically return to 0 because they are trigger bits.
PAGE 311
RL78/G1A CHAPTER 6 TIMER ARRAY UNIT 6.10 Cautions When Using Timer Array Unit 6.10.1 Cautions when using timer output Depends on products, a pin is assigned a timer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status. For details, see 4.5 Register Settings When Using Alternate Function. R01UH0305EJ0200 Rev.2.
PAGE 312
RL78/G1A CHAPTER 7 REAL-TIME CLOCK CHAPTER 7 REAL-TIME CLOCK 7.1 Functions of Real-time Clock The real-time clock has the following features. • Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. • Constant-period interrupt function (period: 0.
PAGE 313
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.2 Configuration of Real-time Clock The real-time clock includes the following hardware. Table 7-1.
PAGE 314
RL78/G1A CHAPTER 7 REAL-TIME CLOCK Figure 7-1.
PAGE 315
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers.
PAGE 316
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the real-time clock is used, be sure to set bit 7 (RTCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
PAGE 317
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the count clock (fRTC) of the real-time clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-3.
PAGE 318
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.3 Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function. The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-4.
PAGE 319
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.4 Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-5.
PAGE 320
RL78/G1A CHAPTER 7 REAL-TIME CLOCK Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) Address: FFF9EH After reset: 00H R/W Symbol <7> <6> 5 <4> <3> 2 <1> <0> RTCC1 WALE WALIE 0 WAFG RIFG 0 RWST RWAIT RWST Wait status flag of real-time clock 0 Counter is operating. 1 Mode to read or write counter value This status flag indicates whether the setting of the RWAIT bit is valid. Before reading or writing the counter value, confirm that the value of this flag is 1.
PAGE 321
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.5 Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the internal counter (16-bit) overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later. Set a decimal value of 00 to 59 to this register in BCD code. The SEC register can be set by an 8-bit memory manipulation instruction.
PAGE 322
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.7 Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later.
PAGE 323
RL78/G1A CHAPTER 7 REAL-TIME CLOCK Table 7-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 7-2. Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 1) Time HOUR Register Time HOUR Register 0 00H 12 a.m. 12H 1 01H 1 a.m. 01H 2 02H 2 a.m. 02H 3 03H 3 a.m. 03H 4 04H 4 a.m. 04H 5 05H 5 a.m. 05H 6 06H 6 a.m. 06H 7 07H 7 a.m. 07H 8 08H 8 a.m. 08H 9 09H 9 a.m.
PAGE 324
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.8 Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
PAGE 325
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.9 Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later. Set a decimal value of 00 to 06 to this register in BCD code. The WEEK register can be set by an 8-bit memory manipulation instruction.
PAGE 326
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.10 Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of fRTC later. Even if the day count register overflows while this register is being written, this register ignores the overflow and is set to the value written.
PAGE 327
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.12 Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the internal counter (16-bit) to the second count register (SEC) (reference value: 7FFFH). The SUBCUD register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-13.
PAGE 328
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.3.13 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected. Figure 7-14.
PAGE 329
RL78/G1A CHAPTER 7 REAL-TIME CLOCK Here is an example of setting the alarm. Time of Alarm Day 12-Hour Display Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour Hour 24-Hour Display Hour Hour 10 1 Minute Minute 10 1 10 1 Minute Minute 10 1 W W W W W W W W W W W W W W 0 1 2 3 4 5 6 Every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 Every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 Every day, 11:59 a.m.
PAGE 330
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4 Real-time Clock Operation 7.4.1 Starting operation of real-time clock Figure 7-19. Procedure for Starting Operation of Real-time Clock Start RTCEN = 1Note 1 RTCE = 0 Setting WUTMMCK0 Setting AMPM, CT2 to CT0 Supplies input clock. Stops counter operation. Sets fRTC Selects 12-/24-hour system and interrupt (INTRTC). Setting SEC Sets second count register. Setting MIN Sets minute count register. Setting HOUR Sets hour count register.
PAGE 331
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after the INTRTC interrupt has occurred. • Shifting to HALT/STOP mode when at least two count clocks (fRTC) have elapsed after setting the RTCE bit to 1 (see Figure 7-20, Example 1).
PAGE 332
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. Figure 7-21. Procedure for Reading Real-time Clock Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Reading SEC Reads second count register. Reading MIN Reads minute count register. Reading HOUR Reads hour count register.
PAGE 333
RL78/G1A CHAPTER 7 REAL-TIME CLOCK Figure 7-22. Procedure for Writing Real-time Clock Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Writing SEC Writes second count register. Writing MIN Writes minute count register. Writing HOUR Writes hour count register. Writing WEEK Writes week count register. Writing DAY Writing MONTH No Writes day count register. Writes month count register.
PAGE 334
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE (alarm operation invalid.) first. Figure 7-23. Alarm processing Procedure Start WALE = 0 Match operation of alarm is invalid. WALIE = 1 alarm match interrupts is valid.. Setting ALARMWM Sets alarm minute register. Setting ALARMWH Sets alarm hour register. Setting ALARMWW Sets alarm week register. Match operation of alarm is valid.
PAGE 335
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.5 1 Hz output of real-time clock Figure 7-24. 1 Hz Output Setting Procedure Start RTCE = 0 Stops counter operation. Setting port Sets P30 = 0 and PM30 = 0 RCLOE1 = 1 Enables output of the RTC1HZ pin (1 Hz). RTCE = 1 Starts counter operation. Output start from RTC1HZ pin Cautions 1. First set the RTCEN bit to 1, while oscillation of the count clock (fSUB) is stable. 2.
PAGE 336
RL78/G1A CHAPTER 7 REAL-TIME CLOCK 7.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the internal counter (16-bit) is calculated by using the following expression. Set the DEV bit to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
PAGE 337
RL78/G1A CHAPTER 7 REAL-TIME CLOCK Correction example 1 Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz – 131.2 ppm) [Measuring the oscillation frequency] The oscillation frequencyNote of each product is measured by outputting about 32.768 kHz from the PCLBUZ0 pin, or by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H). Note See 7.4.
PAGE 338
R01UH0305EJ0200 Rev.2.00 Jul 04, 2013 SEC RSUBC count value 0000H Count start 00 8054 8055 01 0000H 0001H 7FFFH + 56H (86) 7FFFH 19 0000H 0001H 7FFFH 0000H 20 8054H 8055H 39 0000H 0001H 7FFFH + 56H (86) 7FFFH 0000H 40 8054H 8055H 59 0000H 0001H 7FFFH + 56H (86) Figure 7-25.
PAGE 339
RL78/G1A CHAPTER 7 REAL-TIME CLOCK Correction example 2 Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] The oscillation frequencyNote of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H). Note See 7.4.5 1 Hz output of real-time clock for the setting procedure of outputting about 1 Hz from the RTC1HZ pin.
PAGE 340
R01UH0305EJ0200 Rev.2.00 Jul 04, 2013 SEC Counter (16-bit) count value 0000H Count start 00 01 7FDAH 7FDBH 0000H 0001H 7FFFH-24H (36) 7FFFH 19 0000H 0001H 20 7FFFH 0000H 0001H 7FFFH 39 0000H 0001H 40 7FFFH 0000H 0001H 7FFFH 59 0000H 0001H Figure 7-26.
PAGE 341
RL78/G1A CHAPTER 8 INTERVAL TIMER CHAPTER 8 12-BIT INTERVAL TIMER 8.1 Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter’s SNOOZE mode. 8.2 Configuration of 12-bit Interval Timer The interval timer includes the following hardware. Table 8-1.
PAGE 342
RL78/G1A CHAPTER 8 INTERVAL TIMER 8.3 Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. • Peripheral enable register 0 (PER0) • Subsystem clock supply mode control register (OSMC) • Interval timer control register (ITMC) 8.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware.
PAGE 343
RL78/G1A CHAPTER 8 INTERVAL TIMER 8.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the 12-bit interval timer and real-time clock operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption. For details about setting the RTCLPC bit, see CHAPTER 5 CLOCK GENERATOR. The OSMC register can be set by an 8-bit memory manipulation instruction.
PAGE 344
RL78/G1A CHAPTER 8 INTERVAL TIMER 8.3.3 Interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0FFFH. Figure 8-4.
PAGE 345
RL78/G1A CHAPTER 8 INTERVAL TIMER 8.4 12-bit Interval Timer Operation 8.4.1 12-bit interval timer operation timing The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate as a 12-bit interval timer that repeatedly generates interrupt requests (INTIT). When the RINTE bit is set to 1, the 12-bit counter starts counting.
PAGE 346
RL78/G1A CHAPTER 8 INTERVAL TIMER 8.4.
PAGE 347
RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER The number of output pins of the clock output and buzzer output controllers differs, depending on the product. Output pin 25-pin 32, 48, 64-pin PCLBUZ0 √ √ PCLBUZ1 − √ Caution Most of the following descriptions in this chapter use the 64-pin as an example. 9.
PAGE 348
RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-1.
PAGE 349
RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 9-1. Configuration of Clock Output/Buzzer Output Controller Item Control registers Configuration Clock output select registers n (CKSn) Port mode register 14 (PM14) Port register 14 (P14) 9.
PAGE 350
RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 9-2.
PAGE 351
RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.3.2 Registers controlling port functions of pins to be used for clock or buzzer output Using a port pin for clock or buzzer output requires setting of the registers that control the port functions multiplexed on the target pin (port mode register (PMxx), port register (Pxx)). For details, see 4.3.1 Port mode registers (PMxx) and 4.3.2 Port registers (Pxx). Specifically, using a port pin with a multiplexed clock or buzzer output function (e.g.
PAGE 352
RL78/G1A CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 9.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1). 9.4.1 Operation as output pin The PCLBUZn pin is output as the following procedure.
PAGE 353
RL78/G1A CHAPTER 10 WATCHDOG TIMER CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock (fIL). The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
PAGE 354
RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Counter Internal counter (17 bits) Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte. Table 10-2.
PAGE 355
RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 10.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 10-2.
PAGE 356
RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (000C0H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 24).
PAGE 357
RL78/G1A CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT, STOP, and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0 In HALT mode WDSTBYON = 1 Watchdog timer operation stops. Watchdog timer operation continues. In STOP mode In SNOOZE mode If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is cleared to 0 and counting starts.
PAGE 358
RL78/G1A CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows. • If “ACH” is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer is cleared and starts counting again.
PAGE 359
RL78/G1A CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 29/fIL, the window close time and open time are as follows. Setting of Window Open Period 50% 75% 100% Window close time 0 to 20.08 ms 0 to 10.04 ms None Window open time 20.08 to 29.68 ms 10.04 to 29.68 ms 0 to 29.68 ms • Overflow time: 29/fIL (MAX.) = 29/17.25 kHz = 29.68 ms • Window close time: 0 to 29/fIL (MIN.) × (1 − 0.5) = 0 to 29/12.75 kHz × 0.5 = 0 to 20.
PAGE 360
RL78/G1A CHAPTER 11 A/D CONVERTER CHAPTER 11 A/D CONVERTER The number of analog input channels of the A/D converter differs, depending on the product.
PAGE 361
RL78/G1A CHAPTER 11 A/D CONVERTER Various A/D conversion modes can be specified by using the mode combinations below. Trigger mode Software trigger Conversion is started by software manipulation. Hardware trigger no-wait mode Conversion is started by detecting a hardware trigger.
PAGE 362
ADS4 ADS3 ADS1 ADS0 2 A/D converter mode register 1 (ADM1) ADMD Internal bus ADCS Controller FR2 Successive approximation register (SAR) ADTMD1 ADTMD0 ADSCM ADTRS1 ADTRS0 ADTYP AVSS FR1 FR0 LV0 ADREFM bit ADCE A/D converter mode register 0 (ADM0) LV1 Comparison voltage generator A/D conversion result register (ADCR) INTAD Timer trigger signal (INTRTC) Timer trigger signal (INTIT) Timer trigger signal (INTTM01) A/D conversion result upper limit/lower limit comparator AVSS AVREFM/A
PAGE 363
RL78/G1A CHAPTER 11 A/D CONVERTER 11.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI12 and ANI16 to ANI30 pins These are the analog input pins of the 28 channels of the A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
PAGE 364
RL78/G1A CHAPTER 11 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
PAGE 365
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3 Registers Used in A/D Converter The A/D converter is controlled by the following registers.
PAGE 366
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
PAGE 367
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-3.
PAGE 368
RL78/G1A CHAPTER 11 A/D CONVERTER Table 11-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation 0 0 Conversion stopped state 0 1 Conversion standby state 1 0 Setting prohibited 1 1 Conversion-in-progress state Table 11-2.
PAGE 369
RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Conversion operation Conversion standby Software trigger mode ADCS Conversion standby ADCS Trigger standby Note 1 0 is written to ADCS. Conversion operation Conversion standby, trigger standby Conversion stopped A/D power Note 2 supply stabilization wait time 0 is written to ADCS.
PAGE 370
RL78/G1A CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (1/4) (1) 12-bit resolution mode (ADTYP = 0) When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) Mode A/D Converter Mode Register 0 Conversion Number of Conversion Clock (fAD) Conversion (ADM0) Time Clock Conversion Time Selection AVDD = 1.6 to 3.6 V AVDD = 1.6 to 3.6 V AVDD = 1.8 to 3.6 V AVDD = 2.4 to 3.6 V AVDD = 2.7 to 3.
PAGE 371
RL78/G1A CHAPTER 11 A/D CONVERTER Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 29.6.1 or 30.6.1 A/D converter characteristics. 2. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped (ADCS = 0, ADCE = 0). 3. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. 4.
PAGE 372
RL78/G1A CHAPTER 11 A/D CONVERTER Table 11-3.
PAGE 373
RL78/G1A Notes 1. CHAPTER 11 A/D CONVERTER For the second and subsequent conversion in sequential conversion mode and for conversion of the channel specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see Table 11-3 (1/4)). 2. When using ANI16 to ANI30, setting this value is prohibited. Cautions 1.
PAGE 374
RL78/G1A CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (3/4) (3) 8-bit resolution mode (ADTYP = 1) When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) Mode A/D Converter Mode Register 0 Conversion Number of Conversion Clock (fAD) Conversion (ADM0) Time Clock Conversion Time Selection AVDD = 1.6 to 3.6 V AVDD = 1.6 to 3.6 V AVDD = 1.8 to 3.6 V AVDD = 2.4 to 3.6 V AVDD = 2.7 to 3.
PAGE 375
RL78/G1A CHAPTER 11 A/D CONVERTER Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (tCONV) described in 29.6.1 or 30.6.1 A/D converter characteristics. 2. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped (ADCS = 0, ADCE = 0). 3. The above conversion time does not include clock frequency errors. Select conversion time, taking clock frequency errors into consideration. 4.
PAGE 376
RL78/G1A CHAPTER 11 A/D CONVERTER Table 11-3.
PAGE 377
RL78/G1A Notes 1. CHAPTER 11 A/D CONVERTER For the second and subsequent conversion in sequential conversion mode and for conversion of the channel specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see Table 11-3 (3/4)). 2. When using ANI16 to ANI30, setting this value is prohibited. Cautions 1.
PAGE 378
RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ADCS ← 1 or ADS rewrite ADCS Sampling timing INTAD SAR clear Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time R01UH0305EJ0200 Rev.2.
PAGE 379
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-6.
PAGE 380
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.4 A/D converter mode register 2 (ADM2) This register is used to select the + side or - side reference voltage of the A/D converter, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-7.
PAGE 381
RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H R/W Symbol 7 6 5 4 <3> <2> 1 <0> ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP ADRCK Checking the upper limit and lower limit conversion result values 0 The A/D conversion end interrupt request signal (INTAD) is output when the ADLL register ≤ the ADCR register ≤ the ADUL register (AREA1).
PAGE 382
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.5 12-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result. The higher 4 bits are fixed to 0. Each time A/D conversion ends, each time A/D conversion ends, the value of ADSAR [11:0] is stored in the A/D conversion result register (note that whether to store this value is determined by the setting of the ADRCK bit of the ADM2 register and by the settings of the ADUL and ADLL registers).
PAGE 383
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that indicate [11:4] bits of ADCR register. The higher 8 bits of 12-bit resolution are storedNote. The ADCRH register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
PAGE 384
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 11-11.
PAGE 385
RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-11.
PAGE 386
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and A/D conversion end interrupt request signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 11-8).
PAGE 387
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage or − side reference voltage for the A/D converter, an analog input channel (ANIxx), the temperature sensor output voltage, or the internal reference voltage (1.45 V) as the target for A/D conversion. When using as the A/D test function, set as follows. • For zero-scale measurement, select the − side reference voltage as the target for conversion.
PAGE 388
RL78/G1A CHAPTER 11 A/D CONVERTER 11.3.11 Registers controlling port function of analog input pins Set up the registers for controlling the functions of the ports shared with the analog input pins of the A/D converter (port mode registers (PMxx), port mode control registers (PMCxx), and A/D port configuration register (ADPC)). For details, see as follows. • 4.3.1 Port mode registers (PMxx) • 4.3.6 Port mode control registers (PMCxx) • 4.3.7 A/D port configuration register (ADPC).
PAGE 389
RL78/G1A CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. <3> Bit 11 of the successive approximation register (SAR) is set.
PAGE 390
RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-15. Conversion Operation of A/D Converter (Software Trigger Mode) ADCS ← 1 or ADS rewrite Conversion time Sampling time A/D converter operation SAR SAR clear Sampling A/D conversion Undefined ADCR Conversion result Conversion result INTAD In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
PAGE 391
RL78/G1A CHAPTER 11 A/D CONVERTER 11.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI12, ANI16 to ANI30) and the theoretical A/D conversion result (stored in the 12-bit A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( VAIN AVREF × 4096 + 0.5) or (ADCR - 0.5) × where, INT( ): AVREF 4096 ≤ VAIN < (ADCR + 0.
PAGE 392
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 11.7 A/D Converter Setup Flowchart. 11.6.1 Software trigger mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
PAGE 393
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait timeNote, the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).
PAGE 394
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
PAGE 395
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status.
PAGE 396
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait timeNote, the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage).
PAGE 397
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait timeNote, the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage).
PAGE 398
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait timeNote, the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage).
PAGE 399
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait timeNote, the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage).
PAGE 400
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS).
PAGE 401
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS).
PAGE 402
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS).
PAGE 403
RL78/G1A CHAPTER 11 A/D CONVERTER 11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS).
PAGE 404
RL78/G1A CHAPTER 11 A/D CONVERTER 11.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. R01UH0305EJ0200 Rev.2.
PAGE 405
RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.1 Setting up software trigger mode Figure 11-29. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMCx register settings PM register setting ANI0 to ANI12 pins: Set using the ADPC register ANI16 to ANI30 pins: Set using the PMCx register The ports are set to the input mode.
PAGE 406
RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.2 Setting up hardware trigger no-wait mode Figure 11-30. Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMCx register settings PM register setting ANI0 to ANI12 pins: Set using the ADPC register ANI16 to ANI30 pins: Set using the PMCx register The ports are set to the input mode.
PAGE 407
RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.3 Setting up hardware trigger wait mode Figure 11-31. Setting up Hardware Trigger Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMCx register settings PM register setting ANI0 to ANI12 pins: Set using the ADPC register ANI16 to ANI30 pins: Set using the PMCx register The ports are set to the input mode.
PAGE 408
RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.4 Setup when temperature sensor output voltage/internal reference voltage is selected (example for software trigger mode and one-shot conversion mode) Figure 11-32. Setup When Temperature Sensor Output Voltage/Internal Reference Voltage Is Selected Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. • ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
PAGE 409
RL78/G1A CHAPTER 11 A/D CONVERTER 11.7.5 Setting up test mode Figure 11-33. Setting up Test Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. • ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: This is used to specify the select mode. • ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
PAGE 410
RL78/G1A CHAPTER 11 A/D CONVERTER 11.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode function, A/D conversion can be performed without operating the CPU. This is effective for reducing the operating current.
PAGE 411
RL78/G1A CHAPTER 11 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
PAGE 412
RL78/G1A CHAPTER 11 A/D CONVERTER (2) If no interrupt is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is not generated.
PAGE 413
RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-37. Flowchart for Setting up SNOOZE Mode Start of setup PER0 register setting ADPC and PMCx register settings PMx register setting • ADM0 register setting Normal operation • ADM1 register setting • ADM2 register setting • ADUL/ADLL register setting • ADS register setting (The order of the settings is irrelevant.
PAGE 414
RL78/G1A CHAPTER 11 A/D CONVERTER 11.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 12 bits.
PAGE 415
RL78/G1A CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
PAGE 416
RL78/G1A CHAPTER 11 A/D CONVERTER 11.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start operation.
PAGE 417
RL78/G1A CHAPTER 11 A/D CONVERTER Figure 11-44. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREFP, and AVDD or equal to or lower than AVREFM, and AVSS, may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREFP, or AVDD ANI0 to ANI12, ANI16 to ANI30 C = 10 pF to 0.1 μF (5) Analog input (ANIn) pins <1> ANI0 to ANI12 pins (high-accuracy channel) are also used as P20 to P27, and P150 to P154 pins.
PAGE 418
RL78/G1A CHAPTER 11 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may be set just before the ADS register rewrite.
PAGE 419
RL78/G1A CHAPTER 11 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 11-46. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 11-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVDD 2.4 V ≤ AVDD ≤ 3.6 V 1.8 V ≤ AVDD ≤ 3.6 V 1.6 V ≤ AVDD ≤ 3.6 V ANIn pin R1[kΩ] C1[pF] C2[pF] ANI0 to ANI12 7.4 8 6.3 ANI16 to ANI30 12.3 8 7.4 ANI0 to ANI12 11 8 6.3 ANI16 to ANI30 41 8 7.
PAGE 420
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT CHAPTER 12 SERIAL ARRAY UNIT A single serial array unit has up to four serial channels. Each channel can achieve 3-wire serial (CSI), UART, and simplified I2C communication. Function assignment of each channel supported by the RL78/G1A is as shown below.
PAGE 421
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G1A has the following features. 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
PAGE 422
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.1.2 UART (UART0 to UART2) This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
PAGE 423
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.1.3 Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
PAGE 424
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 12-1.
PAGE 425
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-1 shows the block diagram of the serial array unit 0. Figure 12-1.
PAGE 426
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-2 shows the block diagram of the serial array unit 1. Figure 12-2.
PAGE 427
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.2.1 Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are usedNote 1. The shift register cannot be directly manipulated by program. During reception, it converts data input to the serial pin into parallel data, and stores to the lower 8/9 bits of the SDRmn register.
PAGE 428
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-3.
PAGE 429
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers.
PAGE 430
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1. When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
PAGE 431
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0. Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1). The SPSm register can be set by a 16-bit memory manipulation instruction.
PAGE 432
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or simplified I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART mode.
PAGE 433
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-6.
PAGE 434
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7.
PAGE 435
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-7.
PAGE 436
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Caution Be sure to clear bits 3, 6, and 11 to “0”. (Also clear bit 5 of the SCR01, SCR03, or SCR11 register to 0). Be sure to set bit 2 to “1”. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 10, 11, 20, 21) 12.3.5 Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n.
PAGE 437
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-8.
PAGE 438
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn (SSRmn) is cleared to 0. Because the SIRmn register is a trigger register, it is cleared immediately when the corresponding bit of the SSRmn register is cleared.
PAGE 439
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error. The SSRmn register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SSRmn register can be set with an 8-bit memory manipulation instruction with SSRmnL.
PAGE 440
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-10. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H R Note 1 F0140H, F0141H (SSR10), F0142H, F0143H (SSR11) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SSRmn 0 0 0 0 0 0 0 0 0 TSF BFF 0 0 mn mn FEFm n 2 1 FEFm PEF Note 2 n mn 0 OVF mn Framing error detection flag of channel n Note 2 0 No error occurs.
PAGE 441
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately when SEmn = 1. The SSm register can be set by a 16-bit memory manipulation instruction.
PAGE 442
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0.
PAGE 443
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
PAGE 444
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
PAGE 445
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n. The value of the CKOmn bit of this register is output from the serial clock output pin of channel n. The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0).
PAGE 446
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.13 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode and simplifies 2 I C mode. Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn = 1).
PAGE 447
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-17. Examples of Reverse Transmit Data (a) Non-reverse Output (SOLmn = 0) SOLm = 0 output SOUT0n Transmit data (b) Reverse Output (SOLmn = 1) SOLm = 1 output SOUT0n Transmit data (inverted) Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2) R01UH0305EJ0200 Rev.2.
PAGE 448
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.14 Serial standby control register 0 (SSC0) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSC0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSC0 register can be set with an 8-bit memory manipulation instruction with SSC0L. Reset signal generation clears the SSC0 register to 0000H.
PAGE 449
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.15 Input switch control register (ISC) The ISC1 and ISC0 bits of the ISC register are used to realize a LIN-bus communication operation by UART2 in coordination with an external interrupt and the timer array unit. When bit 0 is set to 1, the input signal of the serial data input (RXD2) pin is selected as an external interrupt (INTP0) that can be used to detect a wakeup signal.
PAGE 450
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.16 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. 2 Disable the noise filter of the pin used for CSI or simplified I C communication, by clearing the corresponding bit of this register to 0. Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1.
PAGE 451
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.3.17 Registers controlling port functions of serial input/output pins Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port input mode register (PIMxx), port output mode register (POMxx), port mode control register (PMCxx)). For details, see 4.3.1 Port mode registers (PMxx), 4.3.2 Port registers (Pxx), 4.3.
PAGE 452
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode. 12.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
PAGE 453
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 12-23. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable stopping communication/count by each channel.
PAGE 454
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
PAGE 455
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) are channels 0 to 3 of SAU0 and channels 0 to 3 of SAU1.
PAGE 456
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) performs the following seven types of communication operations. • Master transmission (See 12.5.1.) • Master reception (See 12.5.2.) • Master transmission/reception (See 12.5.3.) • Slave transmission (See 12.5.4.) • Slave reception (See 12.5.5.) • Slave transmission/reception (See 12.5.6.) • SNOOZE mode function (See 12.5.7.) R01UH0305EJ0200 Rev.2.
PAGE 457
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.1 Master transmission Master transmission is that the RL78 microcontroller outputs a transfer clock and transmits data to another device.
PAGE 458
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-24.
PAGE 459
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
PAGE 460
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-25. Initial Setting Procedure for Master Transmission Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
PAGE 461
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-26. Procedure for Stopping Master Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0: to operation stop status) (Essential) Changing setting of the SOEm register Set the SOEmn bit to 0 and stop the output of the target channel.
PAGE 462
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-27. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target No (Essential) Master ready? (slave) or communication operation completed Yes Disable data output and clock output of (Essential) Port manipulation the target channel by setting a port register and a port mode register. (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting.
PAGE 463
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-28.
PAGE 464
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-29. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, see Figure 12-26. (Select Transfer end interrupt) Main routine Set data for transmission and the number of data.
PAGE 465
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-30.
PAGE 466
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-31. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting For the initial setting, see Figure 12-26. (Select buffer empty interrupt) Set data for transmission and the number of data.
PAGE 467
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.2 Master reception Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device.
PAGE 468
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-32.
PAGE 469
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) …The register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 Note Note × × × × (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
PAGE 470
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-33. Initial Setting Procedure for Master Reception Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
PAGE 471
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-34. Procedure for Stopping Master Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
PAGE 472
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-35. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (Essential) Completing master preparations? (Essential) Port manipulation No Yes (slave) or communication operation completed Disable clock output of the target channel by setting a port register and a port mode register.
PAGE 473
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-36.
PAGE 474
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-37. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting For the initial setting, see Figure 12-34.
PAGE 475
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 12-38.
PAGE 476
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-39. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication SAU default setting For the initial setting, see Figure 12-34.
PAGE 477
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.3 Master transmission/reception Master transmission/reception is that the RL78 microcontroller outputs a transfer clock and transmits/receives data to/from other device.
PAGE 478
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-40.
PAGE 479
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
PAGE 480
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-41. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
PAGE 481
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-42. Procedure for Stopping Master Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
PAGE 482
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-43. Procedure for Resuming Master Transmission/Reception Starting setting for resumption (Essential) Completing slave preparations? No Yes (Essential) Port manipulation Wait until stop the communication target (slave) or communication operation completed Disable data output and clock output of the target channel by setting a port register and a port mode register.
PAGE 483
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-44.
PAGE 484
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-45. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, see Figure 12-42.
PAGE 485
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-46.
PAGE 486
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting For the initial setting, see Figure 12-42.
PAGE 487
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.4 Slave transmission Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock being input from another device.
PAGE 488
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-48.
PAGE 489
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
PAGE 490
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-49. Initial Setting Procedure for Slave Transmission Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
PAGE 491
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-50. Procedure for Stopping Slave Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
PAGE 492
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-51. Procedure for Resuming Slave Transmission Starting setting for resumption Completing master preparations? (Essential) No Yes (Selective) Port manipulation Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register. Re-set the register to change the operation (Selective) Changing setting of the SPSm register clock setting.
PAGE 493
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-52.
PAGE 494
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-53. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, see Figure 12-50.
PAGE 495
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-54.
PAGE 496
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-55. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting Main routine Setting transmit data For the initial setting, see Figure 12-50.
PAGE 497
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.5 Slave reception Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being input from another device.
PAGE 498
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-56.
PAGE 499
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) …The Register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 Note Note × × × × (f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
PAGE 500
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-57. Initial Setting Procedure for Slave Reception Starting initial settings Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Setting the SDRmn register Set baud rate setting (bits 15 to 9) to 0000000B.
PAGE 501
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-58. Procedure for Stopping Slave Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0: to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel.
PAGE 502
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-59.
PAGE 503
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 12-60.
PAGE 504
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-61. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting Ready for reception For the initial setting, see Figure 12-58.
PAGE 505
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.6 Slave transmission/reception Slave transmission/reception is that the RL78 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device.
PAGE 506
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-62.
PAGE 507
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21, CSI30, CSI31) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
PAGE 508
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-63. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
PAGE 509
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-64. Procedure for Stopping Slave Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
PAGE 510
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-65. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption (Essential) Completing master preparations? (Essential) Port manipulation No Yes Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register. (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting.
PAGE 511
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 12-66.
PAGE 512
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-67. Flowchart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication SAU default setting Setting transmission/reception data Main routine Enables interrupt Writing transmit data to SIOp (=SDRmn[7:0]) For the initial setting, see Figure 12-64.
PAGE 513
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 12-68.
PAGE 514
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting Main routine Setting transmission/reception data Enables interrupt For the initial setting, see Figure 12-64.
PAGE 515
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.7 SNOOZE mode function SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU operation by detecting SCKp pin input. Only CSIs00 can be specified for asynchronous reception.
PAGE 516
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-71.
PAGE 517
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 12-72.
PAGE 518
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-73.
PAGE 519
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) communication can be calculated by the following expressions.
PAGE 520
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-2.
PAGE 521
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21) communication is described in Figure 12-74. Figure 12-74. Processing Procedure in Case of Overrun Error Software Manipulation Reads serial data register mn (SDRmn).
PAGE 522
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6 Operation of UART (UART0 to UART2) Communication This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
PAGE 523
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT UART0 uses channels 0 and 1 of SAU0. UART1 uses channels 2 and 3 of SAU0. UART2 uses channels 0 and 1 of SAU1.
PAGE 524
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Select any function for each channel. Only the selected function is possible. If UART0 is selected for channels 0 and 1 of unit 0, for example, these channels cannot be used for CSI00 and CSI01. At this time, however, channel 2, 3, or other channels of the same unit can be used for a function other than UART0, such as CSI10, UART1, and IIC10.
PAGE 525
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.1 UART transmission UART transmission is an operation to transmit data from the RL78 microcontroller to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission.
PAGE 526
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-75.
PAGE 527
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-75. Example of Contents of Registers for UART Transmission of UART (UART0 to UART2) (2/2) (e) Serial output register m (SOm) … Sets only the bits of the target channel.
PAGE 528
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-76. Initial Setting Procedure for UART Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
PAGE 529
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-77. Procedure for Stopping UART Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel.
PAGE 530
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-78. Procedure for Resuming UART Transmission Starting setting for resumption Completing master preparations? (Essential) Yes (Selective) Port manipulation No Wait until stop the communication target or communication operation completed Disable data output of the target channel by setting a port register and a port mode register. Re-set the register to change the (Selective) Changing setting of the SPSm register operation clock setting.
PAGE 531
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 12-79.
PAGE 532
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-80. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication SAU default setting For the initial setting, see Figure 12-77. (Select transfer end interrupt) Set data for transmission and the number of data.
PAGE 533
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 12-81.
PAGE 534
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-82. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication <1> SAU default setting For the initial setting, see Figure 12-77. (Select buffer empty interrupt) Setting transmit data Set data for transmission and the number of data.
PAGE 535
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.2 UART reception UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
PAGE 536
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-83.
PAGE 537
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-83. Example of Contents of Registers for UART Reception of UART (UART0 to UART2) (2/2) (e) Serial output register m (SOm) … The register that not used in this mode. 15 14 13 12 0 0 0 0 SOm 11 10 9 8 7 6 5 4 0 0 0 0 CKOm3 CKOm2 CKOm1 CKOm0 Note Note × × × × 3 2 1 0 SOm3 SOm2 SOm1 SOm0 Note Note × × × × 1 0 (f) Serial output enable register m (SOEm) …The register that not used in this mode.
PAGE 538
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-84. Initial Setting Procedure for UART Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Set an operation mode, etc. Setting the SMRmn and SMRmr registers Set a communication format.
PAGE 539
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-86. Procedure for Resuming UART Reception Starting setting for resumption Completing master preparations? (Essential) No Stop the target for communication or wait until completes its communication operation. Yes (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting.
PAGE 540
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-87.
PAGE 541
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-88. Flowchart of UART Reception Starting UART communication SAU default setting Main routine Setting receive data Enables interrupt For the initial setting, see Figure 12-85.
PAGE 542
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the UART to perform reception operations without CPU operation. Only UART0 channel can be set to the SNOOZE mode. When using UARTq in the SNOOZE mode, perform the following steps before entering the STOP mode.
PAGE 543
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-3. UART Reception Baud Rate Setting in the SNOOZE Mode High-speed On- UART Reception Baud Rate Setting in the SNOOZE Mode chip Oscillator (fIH) Baud Rate 4800 bps Operation SDRmn Maximum Minimum Cock [15:9] Permissible Permissible Value Value (fMCK) 32 MHz ± 1.0% Note 24 MHz ± 1.0% Note 16 MHz ± 1.0% Note 12 MHz ± 1.0% Note 8 MHz ± 1.0% Note fCLK/2 fCLK/2 fCLK/2 fCLK/2 fCLK/2 5 5 4 4 3 3 105 2.27% −1.53% 79 1.60% −2.18% 105 2.
PAGE 544
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because EOCm1 = 0, an error interrupt (INTSRE0) is not generated even if a communication error occurs independently of the setting of SSECmn bit. Transfer end interrupt (INTSR0) is generated. Figure 12-89.
PAGE 545
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: error interrupt (INTSRE0) generation enable) Because EOCm1 = 1, SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs. Figure 12-90.
PAGE 546
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-91. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) Setting start No Does TSFmn = 0 on all channels? Yes Normal opetarion <1> Writing 1 to the STmn bit → SEmn = 0 SAU default setting <2> <3> The operation of all channels is also stopped to switch to the STOP mode. Channel 1 is specified for UART reception. Change to the UART reception baud rate in SNOOZE mode (SPSm register and bits 15 to 9 in SDRm1 register).
PAGE 547
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: error interrupt (INTSRE0) generation stop) Because EOCmn = 1, SSECm = 1, an error interrupt (INTSRE0) is not generated when a communication error occurs. Figure 12-92.
PAGE 548
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1) Setting start Does TSFmn = 0 on all channels? No Yes SIRm1 = 0007H Normal operation <1> Writing 1 to the STmn bit → SEmn = 0 SAU default setting <2> Setting SSCm register (SWCm = 1, SSECm = 1) Writing 1 to the SSmn bit <3> → SEmn = 1 Setting interrupt Entered the STOP mode The operation of all channels is also stopped to switch to the STOP mode.
PAGE 549
RL78/G1A Caution CHAPTER 12 SERIAL ARRAY UNIT If the SSECm bit is 1, the PEFm1, FEFm1, and OVFm1 flags are not set when a parity error, framing error, or overrun error occurs and no error interrupt (INTSREq) is generated. Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9 bits). Remarks 1.
PAGE 550
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0 to UART2) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited. Remarks 1.
PAGE 551
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-4.
PAGE 552
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0 to UART2) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. (Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) × 100 − 100 [%] Here is an example of setting a UART baud rate at fCLK = 32 MHz.
PAGE 553
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0 to UART2) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
PAGE 554
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2) communication The procedure for processing errors that occurred during UART (UART0 to UART2) communication is described in Figures 12-95 and 12-96. Figure 12-95.
PAGE 555
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.7 LIN Communication Operation 12.7.1 LIN transmission Of UART transmission, UART2 of the 32, 48, and 64-pin products support LIN communication. For LIN transmission, channel 0 of unit 1 is used.
PAGE 556
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to reduce the cost of an automobile network. Communication of LIN is single-master communication and up to 15 slaves can be connected to one master. The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN. Usually, the master is connected to a network such as CAN (Controller Area Network).
PAGE 557
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-98.
PAGE 558
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.7.2 LIN reception Of UART reception, UART2 of the 32, 48, and 64-pin products support LIN communication. For LIN reception, channel 1 of unit 1 is used. UART Support of LIN communication UART0 Not supported UART1 UART2 Not supported Supported Target channel − − Channel 1 of SAU1 Pins used − − RxD2 Interrupt − − INTSR2 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.
PAGE 559
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-99.
PAGE 560
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-100. Flowchart for LIN Reception Starting LIN communication Status of LIN bus signal and operation of the hardware No Generate INTP0? Wait for wakeup frame signalNote Wakeup signal frame RxD2 pin Edge detection Yes INTP0 The low-level width of RxD2 is measured using TM07 and BF is detected.
PAGE 561
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-101 and figure 12-102 show the configuration of a port that manipulates reception of LIN. The wakeup signal transmitted from the master of LIN is received by detecting an edge of an external interrupt (INTP0). The length of the sync field transmitted from the master can be measured by using the external event capture operation of the timer array unit 0 to calculate a baud-rate error.
PAGE 562
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-102.
PAGE 563
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT The peripheral functions used for the LIN communication operation are as follows. • External interrupt (INTP0); Wakeup signal detection Usage: To detect an edge of the wakeup signal and the start of communication • Channel 7 of timer array unit; Baud rate error detection, break field detection.
PAGE 564
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 2 12.8 Operation of Simplified I C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master.
PAGE 565
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT The channel supporting simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) is channels 0 to 3 of SAU0 and channel 0 and 1 of SAU1.
PAGE 566
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) performs the following four types of communication operations. • Address field transmission (See 12.8.1.) • Data transmission (See 12.8.2.) • Data reception (See 12.8.3.) • Stop condition generation (See 12.8.4.) R01UH0305EJ0200 Rev.2.
PAGE 567
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.1 Address field transmission Address field transmission is a transmission operation that first executes in I2C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame.
PAGE 568
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting 2 Figure 12-103.
PAGE 569
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-103. Example of Contents of Registers for Address Field Transmission of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (2/2) (e) Serial output enable register m (SOEm) 15 14 13 12 11 10 9 8 7 6 5 4 0 0 0 0 0 0 0 0 0 0 0 0 SOEm 3 2 1 0 SOEm3 SOEm2 SOEm1 SOEm0 0/1 Note 0/1 0/1 Note 0/1 SOEmn = 0 until the start condition is generated, and SOEmn = 1 after generation.
PAGE 570
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Operation procedure Figure 12-104. Initial Setting Procedure for Address Field Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format.
PAGE 571
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (3) Processing flow Figure 12-105.
PAGE 572
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 2 Figure 12-106. Flowchart of Simplified I C Address Field Transmission Transmitting address field Default setting Writing 0 to the SOmn bit For the initial setting, see Figure 12-105.
PAGE 573
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.2 Data transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released.
PAGE 574
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-107. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (1/2) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
PAGE 575
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-107. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (2/2) (e) Serial output enable register m (SOEm) … Do not manipulate this register during data transmission/reception.
PAGE 576
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-108. Timing Chart of Data Transmission SSmn SEmn SOEmn “L” “H” “H” Transmit data 1 SDRmn SCLr output SDAr output D7 D6 D5 D4 D3 D2 D1 D0 SDAr input D7 D6 D5 D4 D3 D2 D1 D0 Shift register mn ACK Shift operation INTIICr TSFmn 2 Figure 12-109.
PAGE 577
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.3 Data reception Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. After all data are received to the slave, a stop condition is generated and the bus is released.
PAGE 578
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-110. Example of Contents of Registers for Data Reception of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (1/2) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
PAGE 579
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-110. Example of Contents of Registers for Data Reception of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) (2/2) (e) Serial output enable register m (SOEm) … Do not manipulate this register during data transmission/reception.
PAGE 580
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow Figure 12-111.
PAGE 581
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Figure 12-112. Flowchart of Data Reception Address field transmission completed Data reception completed Stop operation for rewriting SCRmn register. Writing 1 to the STmn bit Writing 0 to the TXEmn bit, and 1 to the RXEmn bit mode of the channel. Operation restart Writing 1 to the SSmn bit Last byte received? Set to receive only the operating No Yes Disable output so that not the ACK response to the last received data.
PAGE 582
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 12-113.
PAGE 583
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.5 Calculating transfer rate The transfer rate for simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication can be calculated by the following expressions. (Transfer rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 Caution SDRmn[15:9] must not be set to 00000000B. Be sure to set a value of 00000001B or greater for SDRmn[15:9]. The duty ratio of the SCL signal output by the simplified I2C is 50%.
PAGE 584
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT Table 12-5.
PAGE 585
RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT 12.8.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication The procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication is described in Figure 12-115 and 12-116. Figure 12-115.
PAGE 586
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA CHAPTER 13 SERIAL INTERFACE IICA 13.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLA0) line and a serial data bus (SDAA0) line.
PAGE 587
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-1.
PAGE 588
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-2 shows a serial bus configuration example. Figure 13-2. Serial Bus Configuration Example Using I2C Bus + VDD + VDD Master CPU1 SDAA0 Slave CPU1 Address 0 SCLA0 Serial data bus Serial clock SDAA0 Slave CPU2 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 R01UH0305EJ0200 Rev.2.
PAGE 589
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 13-1.
PAGE 590
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-4. Format of Slave Address Register 0 (SVA0) Address: F0234H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 SVA0 A6 A5 A4 A3 A2 A1 A0 0Note Note Bit 0 is fixed to 0. (3) SO latch The SO latch is used to retain the SDAA0 pin’s output level.
PAGE 591
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit.
PAGE 592
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3 Registers Controlling Serial Interface IICA Serial interface IICA0 is controlled by the following registers. • Peripheral enable register 0 (PER0) • IICA control register 00 (IICCTL00) • IICA flag register 0 (IICF0) • IICA status register 0 (IICS0) • IICA control register 01 (IICCTL01) • IICA low-level width setting register 0 (IICWL0) • IICA high-level width setting register 0 (IICWH0) • Port mode register 6 (PM6) • Port register 6 (P6) 13.3.
PAGE 593
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.2 IICA control register 00 (IICCTL00) This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations. The IICCTL00 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is set from “0” to “1”. Reset signal generation clears this register to 00H.
PAGE 594
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (1/4) Address: F0230H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTL00 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 2 IICE0 I C operation enable Note 1 0 Stop operation. Reset the IICA status register 0 (IICS0) 1 Enable operation. . Stop internal operation. Be sure to set this bit (1) while the SCLA0 and SDAA0 lines are at high level.
PAGE 595
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable If the WUP0 bit of IICA control register 01 (IICCTL01) is 1, no stop condition interrupt will be generated even if SPIE0 = 1.
PAGE 596
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (3/4) STT0 Notes 1, 2 Start condition trigger 0 Do not generate a start condition. 1 When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: • When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag.
PAGE 597
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-6. Format of IICA Control Register 00 (IICCTL00) (4/4) SPT0 Note Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing • For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the ACKE0 bit has been cleared to 0 and slave has been notified of final reception.
PAGE 598
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.3 IICA status register 0 (IICS0) This register indicates the status of I2C. The IICS0 register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears this register to 00H. Caution Reading the IICS0 register while the address match wakeup function is enabled (WUP0 = 1) in STOP mode is prohibited.
PAGE 599
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (2/3) EXC0 Detection of extension code reception 0 Extension code was not received. 1 Extension code was received.
PAGE 600
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-7. Format of IICA Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected.
PAGE 601
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.4 IICA flag register 0 (IICF0) This register sets the operation mode of I2C and indicates the status of the I2C bus. The IICF0 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT0 clear flag (STCF) and I2C bus status flag (IICBSY) bits are read-only. The IICRSV bit can be used to enable/disable the communication reservation function. The STCEN bit can be used to set the initial value of the IICBSY bit.
PAGE 602
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-8.
PAGE 603
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.5 IICA control register 01 (IICCTL01) This register is used to set the operation mode of I2C and detect the statuses of the SCLA0 and SDAA0 pins. The IICCTL01 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only. Set the IICCTL01 register, except the WUP0 bit, while operation of I2C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0).
PAGE 604
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-9. Format of IICA Control Register 01 (IICCTL01) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) 0 The SCLA0 pin was detected at low level. 1 The SCLA0 pin was detected at high level.
PAGE 605
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.6 IICA low-level width setting register 0 (IICWL0) This register is used to control the low-level width (tLOW) of the SCLA0 pin signal that is output by serial interface IICA and the SDAA0 pin signal. The IICWL0 register can be set by an 8-bit memory manipulation instruction. Set the IICWL0 register while operation of I2C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0). Reset signal generation sets this register to FFH.
PAGE 606
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.3.8 Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set the IICE0 bit (bit 7 of IICA control register 00 (IICCTL00)) to 1 before setting the output mode because the P60/SCLA0 and P61/SDAA0 pins output a low level (fixed) when the IICE0 bit is 0.
PAGE 607
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.4 I2C Bus Mode Functions 13.4.1 Pin configuration The serial clock pin (SCLA0) and the serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 .... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDAA0 .... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices.
PAGE 608
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers (1) Setting transfer clock on master side Transfer clock = fMCK IICWL0 + IICWH0 + fMCK (tR + tF) At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows. (The fractional parts of all setting values are rounded up.) • When the fast mode 0.52 × fMCK Transfer clock 0.48 − tR − tF) × fMCK IICWH0 = ( Transfer clock IICWL0 = • When the normal mode 0.
PAGE 609
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Cautions 1. The fastest operation frequency of the IICA operation clock (fMCK) is 20 MHz (Max.). Set the bit 0 (PRS0) of the IICA control register 01 (IICCTL01) to 1, only when the fCLK exceeds 20 MHz. 2. Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK operation frequency for serial interface IICA is determined according to the mode. Fast mode: fCLK = 3.5 MHz (MIN.) Fast mode plus: fCLK = 10 MHz (MIN.
PAGE 610
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus. Figure 13-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I2C bus’s serial data bus. Figure 13-14.
PAGE 611
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
PAGE 612
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
PAGE 613
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 13-19.
PAGE 614
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 13-20.
PAGE 615
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-20.
PAGE 616
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.7 Canceling wait The I2C usually cancels a wait state by the following processing.
PAGE 617
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 13-2. Table 13-2.
PAGE 618
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.9 Address match detection method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when the address set to the slave address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been received. 13.5.
PAGE 619
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration.
PAGE 620
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Table 13-4.
PAGE 621
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.13 Wakeup function The I2C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set.
PAGE 622
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-23. Flow When Setting WUP0 = 0 Upon Address Match (Including Extension Code Reception) STOP mode state No INTIICA0 = 1? Yes WUP0 = 0 Wait Waits for 5 clocks of fMCK. Reading IICS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
PAGE 623
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-24. When Operating as Master Device After Releasing STOP Mode Other than by INTIICA0 START SPIE0 = 1 WUP0 = 1 Wait Waits for 3 clocks of fMCK. STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICA0. WUP0 = 0 No INTIICA0 = 1? Yes Generates a STOP condition or selects as a slave device.
PAGE 624
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
PAGE 625
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-25 shows the communication reservation timing. Figure 13-25.
PAGE 626
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-27. Communication Reservation Protocol DI SET1 STT0 Define communication reservation Wait (Communication reservation)Note 2 Yes MSTS0 = 0? Sets STT0 flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait timeNote 1 by software.
PAGE 627
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 1) When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
PAGE 628
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.15 Cautions (1) When STCEN = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
PAGE 629
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the RL78/G1A as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
PAGE 630
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 13-28. Master Operation in Single-Master System START Initializing I2C busNote Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 13.3.8 Port mode register 6 (PM6)). Setting port Sets a transfer clock. SVAn ← XXH Sets a local address. IICFn ← 0XH Setting STCENn, IICRSVn = 0 Sets a start condition.
PAGE 631
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 13-29. Master Operation in Multi-Master System (1/4) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 13.3.8 Port mode register 6 (PM6)). Setting port IICWLn, IICWHn ← XXH Selects a transfer clock. SVAn ← XXH Sets a local address. IICFn ← 0XH Setting STCENn and IICRSVn Sets a start condition.
PAGE 632
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (2/4) A Enables reserving communication. Prepares for starting communication (generates a start condition). STT0 = 1 Secure wait timeNote by software. Communication processing Wait No MSTS0 = 1? Yes INTIICA0 interrupt occurs? Yes No Wait state after stop condition was detected and start condition was generated by the communication reservation function.
PAGE 633
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-29. Master Operation in Multi-Master System (4/4) C Writing IICAn INTIICAn interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTSn = 1? No Yes No 2 ACKEn = 1 WTIMn = 0 ACKDn = 1? Yes TRCn = 1? WRELn = 1 No Yes INTIICAn interrupt occurs? Communication processing WTIMn = 1 Starts reception. No Waits for data reception.
PAGE 634
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication.
PAGE 635
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK.
PAGE 636
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match.
PAGE 637
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B 3: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 4: IICS0 = 1000××00B (Sets the SPT0 bit to 1)Note 5: IICS0 = 00000001B Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0
PAGE 638
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 1 3: IICS0 = 1000××00B (Clears the WTIM0 bit to 0Note 2, sets the STT0 bit to 1) 4: IICS0 = 1000×110B 5: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 3 6: IICS0 = 1000××00B (Sets th
PAGE 639
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B 3: IICS0 = 1010×000B (Sets the WTIM0 bit to 1)Note 4: IICS0 = 1010××00B (Sets the SPT0 bit to 1) 5: IICS0 = 00000001B Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0 interrupt request signal.
PAGE 640
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001×110B 2: IICS0 = 0
PAGE 641
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×110B 4: IICS0 = 0001×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK
PAGE 642
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0010×010B 4: IICS0 = 0010×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match addres
PAGE 643
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICSn = 00000×10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not extensio
PAGE 644
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code.
PAGE 645
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0001×110B 4: IICS0 = 0001×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0
PAGE 646
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0010×010B 4: IICS0 = 0010×000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD
PAGE 647
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 00000×10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension
PAGE 648
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result.
PAGE 649
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICS0 = 0101×110B 2: IICS0 = 0001×100B 3: IICS0 = 0001××00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0110×010B 2: IICS0 = 0010×000B 3: IICS0 = 0010×000
PAGE 650
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICS0 = 0110×010B 2: IICS0 = 0010×110B 3: IICS0 = 0010×100B 4: IICS0 = 0010××00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request si
PAGE 651
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICS0 = 0110×010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000000B 3
PAGE 652
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK D7 to Dn ST 1 AD6 to AD0 R/W ACK D7 to D0 2 ACK SP 3 1: IICS0 = 1000×110B 2: IICS0 = 01000110B 3: IICS0
PAGE 653
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK SP 3 1: IICS0 = 1000×110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 1 2 1: IICS0 = 10000110B 2: IICS0 = 01000001B Remark : Always generated : Gener
PAGE 654
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000×100B (Clears the WTIM0 bit to 0) 4: IICS0 = 01000000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0
PAGE 655
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000××00B (Sets the STT0 bit to 1) 4: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 AC
PAGE 656
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000×100B (Clears the WTIM0 bit to 0) 4: IICS0 = 01000100B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 =
PAGE 657
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA 13.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
PAGE 658
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
PAGE 659
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 13-32 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 = 1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0). When the start condition is subsequently detected, the master device enters the master device communication status (MSTS0 = 1).
PAGE 660
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
PAGE 661
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 13-32 are explained below. <3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
PAGE 662
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
PAGE 663
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 13-32 are explained below. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
PAGE 664
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-32.
PAGE 665
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The following describes the operations in Figure 13-32 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps to are performed. These steps return the processing to step , the data transmission step. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device.
PAGE 666
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33.
PAGE 667
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 13-33 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0). When the start condition is subsequently detected, the master device enters the master device communication status (MSTS0 = 1).
PAGE 668
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33.
PAGE 669
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 13-33 are explained below. <3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
PAGE 670
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA Figure 13-33.
PAGE 671
RL78/G1A CHAPTER 13 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 13-33 are explained below. <8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICA0: end of transfer). Because of ACKE0 = 0 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the wait status (WREL0 = 1).
PAGE 672
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. • 16 bits × 16 bits = 32 bits (Unsigned) • 16 bits × 16 bits = 32 bits (Signed) • 16 bits × 16 bits + 32 bits = 32 bits (Unsigned) • 16 bits × 16 bits + 32 bits = 32 bits (Signed) • 32 bits ÷ 32 bits = 32 bits, 32-bits remainder (Unsigned) 14.
PAGE 673
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-1.
PAGE 674
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.2.1 Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator mode, and set the dividend data in the division mode.
PAGE 675
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.2.2 Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator mode, and set the divisor data in the division mode. The MDBH and MDBL registers can be set by a 16-bit manipulation instruction.
PAGE 676
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.2.3 Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode. The MDCH and MDCL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 14-4.
PAGE 677
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows.
PAGE 678
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). 14.3.1 Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator.
PAGE 679
RL78/G1A Notes 1. 2. CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Bits 1 and 2 are read-only bits. The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to multiplication/division data register A (MDAH, MDAL), respectively. Cautions 1.
PAGE 680
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4 Operations of Multiplier and Divider/Multiply-Accumulator 14.4.1 Multiplication (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 00H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>.
PAGE 681
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.2 Multiplication (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 08H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>.
PAGE 682
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.3 Multiply-accumulation (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 40H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). <3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH). <4> Set the multiplicand to multiplication/division data register A (L) (MDAL).
PAGE 683
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 × 3 + 3 = 9 → 32767 × 2 + 4294901762 = 0 (over flow generated)) Operation clock <1> MDUC 00H 40H 44H MDSM L MDCH 0000H MDCL 0000H 0000H 0000H 0003H FFFFH 0009H 0000H 0000H 0002H <8>, <9> MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H 0002H 7FFFH 0003H 0002H 0000H 0006H 0000H FFFEH <10> INTMD MACOF MACSF L <2> <3> <4> R01UH0305EJ0200 Rev.2.
PAGE 684
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.4 Multiply-accumulation (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 48H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). (<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) <4> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (L) (MDCL).
PAGE 685
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) Operation (2 × 3 + (−4) = 2 → 32767 × (−1) + (−2147483647) = −2147450882 (overflow occurs.
PAGE 686
RL78/G1A CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 14.4.5 Division operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 80H. <2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). <3> Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL). <4> Set the divisor (higher 16 bits) to multiplication/division data register B (H) (MDBH).
PAGE 687
R01UH0305EJ0200 Rev.2.
PAGE 688
RL78/G1A CHAPTER 15 DMA CONTROLLER CHAPTER 15 DMA CONTROLLER The RL78/G1A has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed.
PAGE 689
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 15-1. Configuration of DMA Controller Item Configuration • DMA SFR address registers 0, 1 (DSA0, DSA1) Address registers • DMA RAM address registers 0, 1 (DRA0, DRA1) Count register • DMA byte count registers 0, 1 (DBC0, DBC1) Control registers • DMA mode control registers 0, 1 (DMC0, DMC1) • DMA operation control register 0, 1 (DRC0, DRC1) 15.2.
PAGE 690
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.2.2 DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (see Table 15-2) can be set to this register. Set the lower 16 bits of the RAM address. This register is automatically incremented when DMA transfer has been started.
PAGE 691
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.2.3 DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times). Each time DMA transfer has been executed, this register is automatically decremented. By reading this DBCn register during DMA transfer, the remaining number of times of transfer can be learned.
PAGE 692
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. • DMA mode control register n (DMCn) • DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0, 1) 15.3.1 DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source.
PAGE 693
RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-4. Format of DMA Mode Control Register n (DMCn) (2/2) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W Symbol <7> <6> <5> <4> 3 2 1 0 DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 0 or 1) IFCn IFCn IFCn IFCn 3 2 1 0 Trigger signal 0 0 0 0 − Selection of DMA start source Note Trigger contents Disables DMA transfer by interrupt. (Only software trigger is enabled.
PAGE 694
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.3.2 DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1). The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 15-5.
PAGE 695
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.4 Operation of DMA Controller 15.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.
PAGE 696
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn).
PAGE 697
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5 Example of Setting of DMA Controller 15.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. • Consecutive transmission of CSI10 (256 bytes) • DMA channel 0 is used for DMA transfer. • DMA start source: INTCSI10 (software trigger (STG0) only for the first start source) • Interrupt of CSI10 is specified by IFC03 to IFC00 = 1000B.
PAGE 698
RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 44H DRA0 = FB00H DBC0 = 0100H DMC0 = 48H Setting for CSI transfer DST0 = 1 STG0 = 1 DMA0 is started. INTCSI10 occurs. User program processing DMA0 transfer CSI transmission Occurrence of INTDMA0 DST0 = 0Note DEN0 = 0 RETI Hardware operation End Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0.
PAGE 699
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. • Consecutive capturing of A/D conversion results. • DMA channel 1 is used for DMA transfer. • DMA start source: INTAD • Interrupt of A/D is specified by IFC13 to IFC10 = 0001B. • Transfers FFF1EH and FFF1FH (2 bytes) of the 12-bit A/D conversion result register (ADCR) to 512 bytes of FFCE0H to FFEDFH of RAM.
PAGE 700
RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs. User program processing DMA1 transfer INTDMA1 occurs. DST1 = 0Note DEN1 = 0 RETI Hardware operation End Note The DST1 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN1 flag is enabled only when DST1 = 0.
PAGE 701
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below. • Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception. • DMA channel 0 is used for DMA transfer. • DMA start source: Software trigger (DMA transfer on occurrence of an interrupt is disabled.
PAGE 702
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1.
PAGE 703
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes.
PAGE 704
RL78/G1A CHAPTER 15 DMA CONTROLLER Figure 15-11.
PAGE 705
RL78/G1A CHAPTER 15 DMA CONTROLLER 15.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, their priority are DMA channel 0 > DMA channel 1.
PAGE 706
RL78/G1A CHAPTER 15 DMA CONTROLLER (4) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions. • CALL !addr16 • CALL $!addr20 • CALL !!addr20 • CALL rp • CALLT [addr5] • BRK • MOV PSW, #byte • MOV PSW, A • MOV1 PSW. bit, CY • SET1 PSW. bit • CLR1 PSW. bit • POP PSW • BTCLR PSW.
PAGE 707
RL78/G1A CHAPTER 15 DMA CONTROLLER (6) Operation if instructions for accessing the data flash area If the data flash area is accessed after a next instruction execution from start of DMA transfer, a 3-clock wait will be inserted to the next instruction. Instruction 1 DMA transfer Instruction 2 The wait of three clock cycles occurs. MOV A, R01UH0305EJ0200 Rev.2.
PAGE 708
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS CHAPTER 16 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product. 25-pin Maskable interrupts 32-pin 48-pin 64-pin External 5 6 10 13 Internal 24 27 27 27 16.1 Interrupt Function Types The following two types of interrupt functions are used.
PAGE 709
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1.
PAGE 710
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1.
PAGE 711
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-1.
PAGE 712
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1.
PAGE 713
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-1.
PAGE 714
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions.
PAGE 715
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2.
PAGE 716
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2.
PAGE 717
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-2.
PAGE 718
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
PAGE 719
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (2/2) Address: FFFD1H After reset: 00H R/W Symbol <7> 6 <5> 4 3 2 1 <0> IF2H FLIF 0 MDIF 0 0 0 0 PIF11 XXIFX Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Cautions 1. The available registers and bits differ depending on the product.
PAGE 720
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-3.
PAGE 721
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H).
PAGE 722
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-4.
PAGE 723
RL78/G1A 16.3.4 CHAPTER 16 INTERRUPT FUNCTIONS External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge enable registers (EGN0, EGN1) These registers specify the valid edge for INTP0 to INTP11. The EGP0, EGP1, EGN0, and EGN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 16-5.
PAGE 724
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-3.
PAGE 725
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI).
PAGE 726
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.4 Interrupt Servicing Operations 16.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
PAGE 727
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-7.
PAGE 728
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction PSW and PC saved, Instruction jump to interrupt servicing Instruction Interrupt servicing program xxIF 9 clocks Remark 1 clock: 1/fCLK (fCLK: CPU clock) Figure 16-9.
PAGE 729
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
PAGE 730
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Table 16-5.
PAGE 731
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing IE = 0 EI INTyy servicing IE = 0 IE = 0 EI INTxx (PR = 11) INTzz servicing EI INTyy (PR = 10) INTzz (PR = 01) RETI IE = 1 IE = 1 RETI RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place.
PAGE 732
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS Figure 16-10. Examples of Multiple Interrupt Servicing (2/2) Example 3.
PAGE 733
RL78/G1A CHAPTER 16 INTERRUPT FUNCTIONS 16.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. • MOV PSW, #byte • MOV PSW, A • MOV1 PSW. bit, CY • SET1 PSW. bit • CLR1 PSW. bit • RETB • RETI • POP PSW • BTCLR PSW.
PAGE 734
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION CHAPTER 17 KEY INTERRUPT FUNCTION The number of key interrupt input channels differs, depending on the product. Key interrupt input channels 25-pin 32-pin 48-pin 64-pin 0 (4) ch 1 (6) ch 6 ch 10 ch Remarks 1. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). 2. Most of the following descriptions in this chapter use the 64-pin products 17.
PAGE 735
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 17-2. Configuration of Key Interrupt Item Control register Configuration Key return control register (KRCTL) Key return mode registers 0, 1 (KRM0, KRM1) Key return flag register (KRF) Port mode registers 0 to 2, 7, 12, 15 (PM0 to PM2, PM7, PM12, PM15) Peripheral I/O redirection register (PIOR) R01UH0305EJ0200 Rev.2.
PAGE 736
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION Figure 17-1.
PAGE 737
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3 Register Controlling Key Interrupt The key interrupt function is controlled by the following five registers: • Key return control register (KRCTL) • Key return mode registers 0, 1 (KRM0, KRM1) • Key return flag register (KRF) • Port mode registers 0 to 2, 7, 12, and 15 (PM0 to PM2, PM7, PM12, PM15) • Peripheral I/O redirection register (PIOR) 17.3.
PAGE 738
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.2 Key return mode registers 0, 1 (KRM0, KRM1) These registers set the key interrupt mode. The KRM0 and KRM1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H. Figure 17-3.
PAGE 739
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.3 Key return flag register (KRF) This register controls the key interrupt flags (KRF0 to KRF5). The KRF register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 17-4.
PAGE 740
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.4 Port mode registers 0 to 2, 7, 12, 15 (PM0 to PM2, PM7, PM12, PM15) When using P70/KR0 to P77/KR7, P05/KR8, P06/KR9, P00/(KR0) to P04/(KR4), P22/(KR5) to P26/(KR9), P10/(KR0) to P15/(KR5), P120/(KR0), P151/(KR6) to P154/(KR9) as a key input, set the bits corresponding to port mode registers 0 to 2, 7, 12, 15 (PM0 to PM2, PM7, PM12, PM15) to 1.
PAGE 741
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.3.5 Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. Use the PIOR register to assign a port to the function to redirect and enable the function. In addition, can be changed the settings for redirection until its function enable operation.
PAGE 742
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.4 Key Interrupt Operation 17.4.1 When not using the key interrupt flag (KRMD = 0) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR9). The channel to which the valid edge was input can be identified by reading the port register and checking the port level after the key interrupt (INTKR) is generated.
PAGE 743
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION 17.4.2 When using the key interrupt flag (KRMD = 1) A key interrupt (INTKR) is generated when the valid edge specified by the setting of the KREG bit is input to a key interrupt pin (KR0 to KR5). The channels to which the valid edge was input can be identified by reading the key return flag register (KRF) after the key interrupt (INTKR) is generated. If the KRMD bit is set to 1, the INTKR signal is cleared by clearing the corresponding bit in the KRF register.
PAGE 744
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION The operation when a valid edge is input to multiple key interrupt input pins is shown in Figure 17-10 below. A falling edge is also input to the KR1 and KR6 pins after a falling edge was input to the KR0 pin (when KREG = 0). The KRF1 bit is set when the KRF0 bit is cleared. A key interrupt (INTKR) is therefore generated one clock (fCLK) after the KRF0 bit is cleared (<1> in the figure).
PAGE 745
RL78/G1A CHAPTER 17 KEY INTERRUPT FUNCTION The operation when a valid edge is input to the KR6 to KR9 pins without generating a key interrupt (INTKR) is shown in Figure 17-11 below. A falling edge is also input to the KR1 and KR6 pins after a falling edge was input to the KR0 pin (when KREG = 0). The KR1 pin becomes high level when the KRF0 bit is cleared, but because the KRF1 bit is set, a key interrupt (INTKR) is generated one clock (fCLK) after the KRF0 bit is cleared (<1> in the figure).
PAGE 746
RL78/G1A CHAPTER 18 STANDBY FUNCTION CHAPTER 18 STANDBY FUNCTION 18.1 Standby Function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the highspeed system clock oscillator, high-speed on-chip oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.
PAGE 747
RL78/G1A CHAPTER 18 STANDBY FUNCTION 18.2 Registers Controlling Standby Function The registers which control the standby function are described below. • Subsystem clock supply mode control register (OSMC) • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For details of registers described above, see CHAPTER 5 CLOCK GENERATOR.
PAGE 748
RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-1.
PAGE 749
RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-1.
PAGE 750
RL78/G1A CHAPTER 18 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-1.
PAGE 751
RL78/G1A CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-2.
PAGE 752
RL78/G1A CHAPTER 18 STANDBY FUNCTION Figure 18-2.
PAGE 753
RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-2.
PAGE 754
RL78/G1A CHAPTER 18 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 18-3.
PAGE 755
RL78/G1A CHAPTER 18 STANDBY FUNCTION Figure 18-3.
PAGE 756
RL78/G1A CHAPTER 18 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 18-4.
PAGE 757
RL78/G1A CHAPTER 18 STANDBY FUNCTION 18.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSIp, UARTq, or the A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock. When using CSIp or UARTq in the SNOOZE mode, set the SWCm bit of the serial standby control register m (SSCm) to 1 immediately before switching to the STOP mode. For details, see 12.3 Registers Controlling Serial Array Unit.
PAGE 758
RL78/G1A CHAPTER 18 STANDBY FUNCTION Table 18-3.
PAGE 759
RL78/G1A CHAPTER 18 STANDBY FUNCTION (2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode Figure 18-5.
PAGE 760
RL78/G1A CHAPTER 19 RESET FUNCTION CHAPTER 19 RESET FUNCTION The following seven operations are available to generate a reset signal.
PAGE 761
R01UH0305EJ0200 Rev.2.00 Jul 04, 2013 Set Clear Clear Set WDTRF 2. LVIS: Voltage detection level register Remarks 1. LVIM: Voltage detection register Caution An LVD circuit internal reset does not reset the LVD circuit.
PAGE 762
RL78/G1A CHAPTER 19 RESET FUNCTION 19.1 Timing of Reset Operation This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts. Figure 19-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization High-speed on-chip oscillator clock Starting X1 oscillation is specified by software.
PAGE 763
RL78/G1A Notes 1. CHAPTER 19 RESET FUNCTION When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummyoutput as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a reset signal to an external device, set P130 to high-level output by software. 2. Reset times (times for release from the external reset state) After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use. 0.
PAGE 764
RL78/G1A CHAPTER 19 RESET FUNCTION 19.2 States of Operation During Reset Periods Table 19-1 shows the states of operation during reset periods. Table 19-2 shows the states of the hardware after receiving a reset signal. Table 19-1. States of Operation During Reset Period Item During Reset Period System clock Main system clock Subsystem clock Clock supply to the CPU is stopped.
PAGE 765
RL78/G1A Remark CHAPTER 19 RESET FUNCTION fIH: High-speed on-chip oscillator clock fX: X1 oscillation clock fEX: External main system clock fXT: XT1 oscillation clock fEXS: External subsystem clock fIL: Low-speed on-chip oscillator clock Table 19-2. State of Hardware After Receiving a Reset Signal Hardware After Reset Note Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set.
PAGE 766
RL78/G1A CHAPTER 19 RESET FUNCTION 19.3 Register for Confirming Reset Source 19.3.1 Reset control flag register (RESF) Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF, IAWRF, and LVIRF flags.
PAGE 767
RL78/G1A CHAPTER 19 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 19-3. Table 19-3.
PAGE 768
RL78/G1A CHAPTER 19 RESET FUNCTION Figure 19-5. Procedure for Checking Reset Source After reset acceptance Read the RESF register (clear the RESF register) and store the value of the RESF register in any RAM.
PAGE 769
RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT CHAPTER 20 POWER-ON-RESET CIRCUIT 20.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions. • Generates internal reset signal at power on. The reset signal is released when the supply voltage (VDD) exceeds the detection voltage (VPOR). Note that the reset state must be retained until the operating voltageNote becomes in the range defined in 29.4 or 30.4 AC Characteristics.
PAGE 770
RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT 20.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 20-1. Figure 20-1. Block Diagram of Power-on-reset Circuit VDD VDD + Internal reset signal − Reference voltage source 20.3 Operation of Power-on-reset Circuit The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below. R01UH0305EJ0200 Rev.2.
PAGE 771
RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/3) (1) When the externally input reset signal on the RESET pin is used Supply voltage (VDD) Note 5 Note 5 Lower limit voltage for guaranteed operation VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
PAGE 772
RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (2) LVD interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (VDD) Note 3 VLVDH VLVDL Lower limit voltage for guaranteed operation VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
PAGE 773
RL78/G1A CHAPTER 20 POWER-ON-RESET CIRCUIT Figure 20-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3) (3) LVD reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1) Supply voltage (VDD) VLVD Lower limit voltage for guaranteed operation VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
PAGE 774
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR CHAPTER 21 VOLTAGE DETECTOR 21.1 Functions of Voltage Detector The operation mode and detection voltages (VLVDH, VLVDL, VLVD) for the voltage detector is set by using the option byte (000C1H). The voltage detector (LVD) has the following functions. • The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL, VLVD), and generates an internal reset or interrupt request signal.
PAGE 775
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 21-1. Figure 21-1.
PAGE 776
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-2.
PAGE 777
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 00H/01H/81HNote 1. Figure 21-3.
PAGE 778
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Table 21-1. Format of User Option Byte (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt & reset mode) Detection voltage VLVDH VPOC2 VLVDL VPOC1 VPOC0 LVIS1 LVIS0 Rising edge Falling edge Falling edge 1.77 V 1.73 V 1.63 V 1.88 V 1.84 V 0 1 2.92 V 2.86 V 0 0 1.98 V 1.94 V 1 0 2.09 V 2.04 V 0 1 3.13 V 3.06 V 0 0 2.61 V 2.
PAGE 779
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Table 21-1. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode) Detection voltage Option byte setting value VPOC2 VLVD Rising edge Falling edge 1.67 V 1.63 V 1.77 V VPOC0 LVIS1 LVIS0 0 0 1 1 1.73 V 0 0 1 0 1.88 V 1.84 V 0 1 1 1 1.98 V 1.94 V 0 1 1 0 2.09 V 2.04 V 0 1 0 1 2.50 V 2.
PAGE 780
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.4 Operation of Voltage Detector 21.4.1 When used as reset mode Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. The operation is started in the following initial setting state when the reset mode is set.
PAGE 781
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Figure 21-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (VDD) VLVD Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
PAGE 782
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.4.2 When used as interrupt mode Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt mode is set.
PAGE 783
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Figure 21-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Note 2 Supply voltage (VDD) Note 2 VLVD Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time HNote 1 LVIMK flag (interrupt MASK) (set by software) Cleared by software Cleared LVIF flag LVIMD flag LVILV flag H INTLVI LVIIF flag LVD reset signal POR reset signal Internal reset signal Notes 1. 2.
PAGE 784
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.4.3 When used as interrupt & reset mode Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (VLVDH, VLVDL) by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt & reset mode is set.
PAGE 785
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask, determine that a condition of VDD becomes VDD ≥ VLVDH, clear LVIMD bit to 0, and the MCU shift to normal operation. Supply voltage (VDD) VLVDH VLVDL Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
PAGE 786
RL78/G1A Notes 1. 2. CHAPTER 21 VOLTAGE DETECTOR The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 21-7 Processing Procedure After an Interrupt Is Generated. 3. After a reset is released, perform the processing according to Figure 21-8 Initial Setting of Interrupt and Reset Mode. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0305EJ0200 Rev.2.
PAGE 787
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR Figure 21-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of VDD is VDD < VLVDH after releasing the mask, a reset is generated because of LVIMD = 1 (reset mode). Supply voltage (VDD) VLVDH VLVDL Lower limit of operation voltage VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.
PAGE 788
RL78/G1A Notes 1. 2. CHAPTER 21 VOLTAGE DETECTOR The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 21-7 Processing Procedure After an Interrupt Is Generated. 3. After a reset is released, perform the processing according to Figure 21-8 Initial Setting of Interrupt and Reset Mode. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage Figure 21-7.
PAGE 789
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400 μs or 5 clocks of fIL is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0) clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the LVIMD bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD.
PAGE 790
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR 21.5 Cautions for Voltage Detector (1) Voltage fluctuation when power is supplied In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVD detection voltage, the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
PAGE 791
RL78/G1A CHAPTER 21 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has been generated. In the same way, there is also some delay from the time LVD detection voltage (VLVD) ≤ supply voltage (VDD) until the time LVD reset has been released (see Figure 21-10). Figure 21-10.
PAGE 792
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS CHAPTER 22 SAFETY FUNCTIONS 22.1 Overview of Safety Functions The following safety functions are provided in the RL78/G1A to comply with the IEC60730 and IEC61508 safety standards. These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is detected. (1) Flash memory CRC operation function (high-speed CRC, general-purpose CRC) This detects data errors in the flash memory by performing CRC operations.
PAGE 793
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.2 Registers Used by Safety Functions The safety functions use the following registers for each function.
PAGE 794
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Figure 22-1. Format of Flash Memory CRC Control Register (CRC0CTL) Address: F02F0H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CRC0CTL CRC0EN 0 FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 CRC0EN Control of CRC ALU operation 0 Stop the operation. 1 Start the operation according to HALT instruction execution.
PAGE 795
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Figure 22-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits ; Set CRC operation range. ; Copy the HALT and RET instructions to the ; RAM to execute in the RAM. ; Initialize the 10 bytes after the RET instruction.
PAGE 796
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.2 CRC operation function (general-purpose CRC) In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the CPU is operating. In the RL78/G1A, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area.
PAGE 797
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.2.2 CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register. The CRCD register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 22-5.
PAGE 798
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.3 RAM parity error detection function The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/G1A’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error occurs. 22.3.3.
PAGE 799
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Figure 22-8. Flowchart of RAM Parity Check Start of check RPERF = 1Note Yes No RPERDIS = 1 Disable parity error reset. Check RAM. Check RAM. Parity error generated? No RPEF = 1 RPERDIS = 0 Note Yes Parity error generation checked No Yes Internal reset generated Read RAM. Normal operation Enable parity error reset. RAM failure processing To check internal reset status using a RAM parity error, see CHAPTER 19 RESET FUNCTION.
PAGE 800
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space. If the RAM guard function is specified, writing to the specified RAM space is disabled, but reading from the space can be carried out as usual. 22.3.4.
PAGE 801
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error function.
PAGE 802
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed. The illegal memory access detection function applies to the areas indicated by NG in Figure 22-11. Figure 22-11.
PAGE 803
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Products Code Flash Memory RAM Detected Lowest Address for (00000H to xxxxxH) (zzzzzH to FFEFFH) Read/Instruction Fetch (Execution) (yyyyyH) R5F10ExA (x = 8, B, G) R5F10ExC (x = 8, B, G, ,L) R5F10ExD (x = 8, B, G, L) R5F10ExE (x = 8, B, G, L) 16384 × 8 bit 2048 × 8 bit (00000H to 03FFFH) (FF700H to FFEFFH) 32768 × 8 bit 2048 × 8 bit (00000H to 07FFFH) (FF700H to FFEFFH) 49152 × 8 bit 3072 × 8 bit (00000H to 0BFFFH) (FF300H to FFEFFH) 65536 × 8 bi
PAGE 804
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (fCLK) and measuring the pulse width of the input signal to channel 5 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined.
PAGE 805
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.7.1 Timer input select register 0 (TIS0) The TIS0 register is used to select the timer input of channel 5 of the timer array unit 0 (TAU0). The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 22-14.
PAGE 806
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function checks whether or not the A/D converter is operating normally by executing A/D conversions of the A/D converter’s positive and negative reference voltages, analog input channel (ANI), temperature sensor output voltage, and the internal reference voltage. For details of the check method, see the safety function (A/D test) application note (R01AN0955).
PAGE 807
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Figure 22-15. Configuration of A/D Test Function • ADISS • ADS4 to ADS0 ANI0/AVREFP ANI1/AVREFM • ADTES1, ADTES0 ANIxx ANIxx Temperature sensorNote Internal reference voltage (1.45 V)Note + side reference voltage of AD converter AVDD • ADREFP1, ADREFP0 A/D converter − side reference voltage of AD converter AVSS • ADREFM Note This setting can be used only in HS (high-speed main) mode. R01UH0305EJ0200 Rev.2.
PAGE 808
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS 22.3.8.1 A/D test register (ADTES) This register is used to select the A/D converter’s positive reference voltage, A/D converter’s negative reference voltage, analog input channel (ANIxx), temperature sensor output voltage, or internal reference voltage (1.45 V) as the target of A/D conversion. When using the A/D test function, specify the following settings: • Select negative reference voltage as the target of A/D conversion for zero-scale measurement.
PAGE 809
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Figure 22-17.
PAGE 810
RL78/G1A CHAPTER 22 SAFETY FUNCTIONS Cautions 1. Be sure to clear bits 5 and 6 to 0. 2. Select input mode for the ports which are set to analog input with the ADPC and PMC registers, using the port mode registers 0 to 5, 7, 12, and 15 (PM0 to PM5, PM7, PM12, and PM15). 3. Do not use the ADS register to set the pins which should be set as digital I/O with the A/D port configuration register (ADPC). 4.
PAGE 811
RL78/G1A CHAPTER 23 REGULATOR CHAPTER 23 REGULATOR 23.1 Regulator Overview The RL78/G1A contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage. REGC VSS Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
PAGE 812
RL78/G1A CHAPTER 24 OPTION BYTE CHAPTER 24 OPTION BYTE 24.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the RL78/G1A form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H). Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set. For the bits to which no function is allocated, do not change their initial values.
PAGE 813
RL78/G1A CHAPTER 24 OPTION BYTE (3) 000C2H/010C2H { Setting of flash operation mode • LV (low voltage main) mode • LS (low speed main) mode • HS (high speed main) mode { Setting of the frequency of the high-speed on-chip oscillator • Select from 32 MHz/24 MHz/16 MHz/12 MHz/8 MHz/6 MHz/4 MHz/3 MHz/2 MHz/1 MHz (TYP.). Caution Set the same value as 000C2H to 010C2H when the boot swap operation is used because 000C2H is replaced by 010C2H. 24.1.
PAGE 814
RL78/G1A CHAPTER 24 OPTION BYTE 24.2 Format of User Option Byte The format of user option byte is shown below. Figure 24-1. Format of User Option Byte (000C0H/010C0H) Note 1 Address: 000C0H/010C0H 7 6 5 4 3 2 1 0 WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTINIT Use of interval interrupt of watchdog timer 0 Interval interrupt is not used. 1 Interval interrupt is generated when 75% + 1/2fIL of the overflow time is reached.
PAGE 815
RL78/G1A CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt & reset mode) Detection voltage VLVDH VLVDL VPOC2 VPOC1 VPOC0 LVIS1 Falling edge Falling edge 1.77 V 1.73 V 1.63 V 1 0 1.88 V 1.84 V 0 1 2.92 V 2.86 V 0 0 1.98 V 1.94 V 1 0 2.09 V 2.04 V 0 1 3.13 V 3.06 V 0 0 2.61 V 2.55 V 2.71 V 2.65 V 2.
PAGE 816
RL78/G1A CHAPTER 24 OPTION BYTE Figure 24-2. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 1 LVIS1 LVIS0 LVIMDS1 LVIMDS0 • LVD setting (interrupt mode) Detection voltage Option byte setting value VPOC2 VLVD Rising edge Falling edge 1.67 V 1.63 V 1.77 V 0 VPOC0 LVIS1 LVIS0 0 0 1 1 1.73 V 0 0 1 0 1.88 V 1.84 V 0 1 1 1 1.98 V 1.94 V 0 1 1 0 2.09 V 2.04 V 0 1 0 1 2.50 V 2.
PAGE 817
RL78/G1A CHAPTER 24 OPTION BYTE Figure 24-3. Format of Option Byte (000C2H/010C2H) Note Address: 000C2H/010C2H 7 6 5 4 3 2 1 0 CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating frequency range Operating voltage range 0 0 LV (low voltage main) mode 1 to 4 MHz 1.6 to 3.6 V 1 0 LS (low speed main) mode 1 to 8 MHz 1.8 to 3.6 V 1 1 HS (high speed main) mode 1 to 16 MHz 2.4 to 3.6 V 1 to 32 MHz 2.7 to 3.
PAGE 818
RL78/G1A CHAPTER 24 OPTION BYTE 24.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 24-4. Format of On-chip Debug Option Byte (000C3H/010C3H) Note Address: 000C3H/010C3H 7 6 5 4 3 2 1 0 OCDENSET 0 0 0 0 1 0 OCDERSD OCDENSET OCDERSD 0 0 Control of on-chip debug operation Disables on-chip debug operation. 0 1 Setting prohibited 1 0 Enables on-chip debugging.
PAGE 819
RL78/G1A CHAPTER 24 OPTION BYTE 24.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the link option, in addition to describing to the source. When doing so, the contents set by using the link option take precedence, even if descriptions exist in the source, as mentioned below. A software description example of the option byte setting is shown below.
PAGE 820
RL78/G1A CHAPTER 25 FLASH MEMORY CHAPTER 25 FLASH MEMORY The RL78 microcontroller incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data.
PAGE 821
RL78/G1A CHAPTER 25 FLASH MEMORY The following methods for programming the flash memory are available. The code flash memory can be rewritten to through serial programming using a flash memory programmer or an external device (UART communication), or through self-programming. • Serial programming using flash memory programmer (see 25.4) Data can be written to the flash memory on-board or off-board by using a dedicated flash memory programmer.
PAGE 822
RL78/G1A CHAPTER 25 FLASH MEMORY 25.1 Serial Programming Using Flash Memory Programmer The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78 microcontroller. • PG-FP5, FL-PR5 • E1 on-chip debugging emulator Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
PAGE 823
RL78/G1A CHAPTER 25 FLASH MEMORY Table 25-1. Wiring between RL78/G1A and Dedicated Flash Memory Programmer Pin Configuration of Dedicated Flash Memory Programmer I/O Signal Name Pin Name Pin No.
PAGE 824
RL78/G1A CHAPTER 25 FLASH MEMORY 25.1.1 Programming environment The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below. Figure 25-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 VDD E1 EVDDNote RS-232C VSS, EVSSNote USB RESET Dedicated flash TOOL0 (dedicated single-line UART) memory programmer RL78 microcontroller Host machine Note 64-pin product only.
PAGE 825
RL78/G1A CHAPTER 25 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See each manual of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details. Table 25-2.
PAGE 826
RL78/G1A CHAPTER 25 FLASH MEMORY 25.2.2 Communication mode Communication between the external device and the RL78 microcontroller is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78 microcontroller. Transfer rate: 1 M, 500 k, 250 k, 115.2kbps Figure 25-4.
PAGE 827
RL78/G1A CHAPTER 25 FLASH MEMORY 25.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
PAGE 828
RL78/G1A CHAPTER 25 FLASH MEMORY 25.3.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to either VDD or EVDD0, or VSS or EVSS0, via a resistor. 25.3.4 REGC pin Connect the REGC pin to GND via a capacitor having excellent characteristics (0.
PAGE 829
RL78/G1A CHAPTER 25 FLASH MEMORY 25.4 Serial Programming Method 25.4.1 Serial programming procedure The following figure illustrates a flow for rewriting the code flash memory through serial programming. Figure 25-6. Code Flash Memory Manipulation Procedure Start Controlling TOOL0 pin and RESET pin Flash memory programming mode is set Manipulate code flash memory End? No Yes End R01UH0305EJ0200 Rev.2.
PAGE 830
RL78/G1A CHAPTER 25 FLASH MEMORY 25.4.2 Flash memory programming mode To rewrite the contents of the code flash memory through serial programming, specify the flash memory programming mode. To enter the mode, set as follows. Connect the RL78 microcontroller to a dedicated flash memory programmer. Communication from the dedicated flash memory programmer is performed to automatically switch to the flash memory programming mode.
PAGE 831
RL78/G1A CHAPTER 25 FLASH MEMORY There are two flash memory programming modes: wide voltage mode and full speed mode. The supply voltage value applied to the microcontroller during write operations and the setting information of the user option byte for setting of the flash memory programming mode determine which mode is selected. When a dedicated flash memory programmer is used for serial programming, setting the voltage on GUI selects the mode automatically. Table 25-5.
PAGE 832
RL78/G1A CHAPTER 25 FLASH MEMORY 25.4.3 Selecting communication mode Communication modes of the RL78 microcontroller are as follows. Table 25-6.
PAGE 833
RL78/G1A CHAPTER 25 FLASH MEMORY Product information (such as product name and firmware version) can be obtained by executing the “Silicon Signature” command. Table 25-8 is a list of signature data and Table 25-9 shows an example of signature data. Table 25-8.
PAGE 834
RL78/G1A CHAPTER 25 FLASH MEMORY 25.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) The following shows the processing time for each command (reference value) when PG-FP5 is used as a dedicated flash memory programmer. Table 25-10. Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) PG-FP5 Command Code Flash 16 KB 32 KB 48 KB 64 KB Erasing 1s 1s 1s 1.5 s Writing 1.5 s 1.5 s 2s 2.5 s Verification 1.5 s 1.
PAGE 835
RL78/G1A CHAPTER 25 FLASH MEMORY 25.6 Self-Programming The RL78 microcontroller supports a self-programming function that can be used to rewrite the code flash memory via a user program. Because this function allows a user application to rewrite the code flash memory by using the flash selfprogramming library, it can be used to upgrade the program in the field. Cautions 1. The self-programming function cannot be used when the CPU operates with the subsystem clock. 2.
PAGE 836
RL78/G1A CHAPTER 25 FLASH MEMORY 25.6.1 Self-programming procedure The following figure illustrates a flow for rewriting the code flash memory by using a flash self-programming library. Figure 25-8.
PAGE 837
RL78/G1A CHAPTER 25 FLASH MEMORY 25.6.2 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot area, by self-programming, write a new boot program to boot cluster 1 in advance.
PAGE 838
RL78/G1A CHAPTER 25 FLASH MEMORY Figure 25-10.
PAGE 839
RL78/G1A CHAPTER 25 FLASH MEMORY 25.6.3 Flash shield window function The flash shield window function is provided as one of the security functions for self-programming. It disables writing to and erasing areas outside the range specified as a window only during self-programming. The window range can be set by specifying the start and end blocks. The window range can be set or changed during both serial programming and self-programming.
PAGE 840
RL78/G1A CHAPTER 25 FLASH MEMORY 25.7 Security Settings The RL78 microcontroller supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. • Disabling block erase Execution of the block erase command for a specific block in the flash memory is prohibited during serial programming.
PAGE 841
RL78/G1A CHAPTER 25 FLASH MEMORY Table 25-12. Relationship Between Enabling Security Function and Command (1) During serial programming Valid Security Executed Command Block Erase Write Note Prohibition of block erase Blocks cannot be erased. Can be performed. Prohibition of writing Blocks can be erased. Cannot be performed. Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Note Confirm that no data has been written to the write area.
PAGE 842
RL78/G1A CHAPTER 25 FLASH MEMORY 25.8 Data Flash 25.8.1 Data flash overview An overview of the data flash memory is provided below. • The user program can rewrite the data flash memory by using the data flash library. For details, refer to the RL78 Family Data Flash Library User’s Manual. • The data flash memory can also be rewritten to through serial programming using the dedicated flash memory programmer or an external device. • The data flash can be erased in 1-block (1 KB) units.
PAGE 843
RL78/G1A CHAPTER 25 FLASH MEMORY 25.8.3 Procedure for accessing data flash memory The data flash memory is stopped after a reset ends. To access the data flash, make initial settings according to the following procedure. <1> Set bit 0 (DFLEN) of the data flash control register (DFLCTL) to 1. <2> Wait for the setup to finish for software timer, etc. The time setup takes differs for each flash operation mode for the main clock.
PAGE 844
RL78/G1A CHAPTER 26 ON-CHIP DEBUG FUNCTION CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.1 Connecting E1 On-Chip Debugging Emulator The RL78 microcontroller uses the VDD, RESET, TOOL0, and VSS pins to communicate with the host machine via an E1 on-chip debugging emulator. Serial communication is performed by using a single-line UART that uses the TOOL0 pin. Caution The RL78 microcontroller has an on-chip debug function, which is provided for development and evaluation.
PAGE 845
RL78/G1A CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.2 On-Chip Debug Security ID The RL78 microcontroller has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 24 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content.
PAGE 846
RL78/G1A CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-2.
PAGE 847
RL78/G1A CHAPTER 27 BCD CORRECTION CIRCUIT CHAPTER 27 BCD CORRECTION CIRCUIT 27.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ). 27.
PAGE 848
RL78/G1A CHAPTER 27 BCD CORRECTION CIRCUIT 27.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1> The BCD code value to which addition is performed is stored in the A register.
PAGE 849
RL78/G1A CHAPTER 27 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register.
PAGE 850
RL78/G1A CHAPTER 28 INSTRUCTION SET CHAPTER 28 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Microcontrollers User’s Manual: Software (R01US0015). 28.1 Conventions Used in Operation List 28.1.
PAGE 851
RL78/G1A CHAPTER 28 INSTRUCTION SET 28.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 28-2.
PAGE 852
RL78/G1A CHAPTER 28 INSTRUCTION SET 28.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 28-3. Symbols in “Flag” Column Symbol Change of Flag Value (Blank) Unchanged 0 Cleared to 0 1 Set to 1 × R Set/cleared according to the result Previously saved value is restored 28.1.
PAGE 853
RL78/G1A CHAPTER 28 INSTRUCTION SET 28.2 Operation List Table 28-5.
PAGE 854
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 855
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 856
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 857
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 858
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 859
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 860
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 861
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 862
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 863
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 864
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 865
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 866
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Group Bit Clocks Clocks Note 1 Note 2 Flag Z AC CY CY, A.bit 2 1 − CY ← CY ∨ A.bit × CY, PSW.bit 3 1 − CY ← CY ∨ PSW.bit × CY, saddr.bit 3 1 − CY ← CY ∨ (saddr).bit × CY, sfr.bit 3 1 − CY ← CY ∨ sfr.bit × CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit × CY, ES:[HL].bit 3 2 5 CY ← CY ∨ (ES, HL).bit × A.bit 2 1 − A.bit ← 1 PSW.bit 3 4 − PSW.bit ← 1 !addr16.
PAGE 867
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 868
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5.
PAGE 869
RL78/G1A CHAPTER 28 INSTRUCTION SET Table 28-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Group Condition Note 1 BF saddr.bit, $addr20 al branch sfr.bit, $addr20 A.bit, $addr20 PSW.bit, $addr20 [HL].bit, $addr20 ES:[HL].bit, Clocks Clocks Note 2 Z Note 3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 0 Note 3 − PC ← PC + 4 + jdisp8 if sfr.bit = 0 Note 3 − PC ← PC + 3 + jdisp8 if A.bit = 0 3/5 Note 3 − PC ← PC + 4 + jdisp8 if PSW.
PAGE 870
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) This chapter describes the following electrical specifications.
PAGE 871
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Symbols Conditions Ratings Unit VDD −0.5 to +6.5 V EVDD0 −0.5 to +6.5 V AVDD −0.5 to +4.6 V −0.3 to AVDD +0.3 Note 3 AVREFP EVSS0 −0.5 to +0.3 AVSS −0.5 to +0.3 V V −0.3 to AVDD +0.3 AVREFM V Note 3 V and AVREFM ≤ AVREFP REGC pin input voltage VIREGC REGC −0.3 to +2.8 V and −0.3 to VDD +0.
PAGE 872
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Output current, high Symbols IOH1 Conditions Per pin P00 to P06, P10 to P16, P30, P31, Ratings Unit −40 mA −70 mA −100 mA −0.1 mA −1.3 mA 40 mA 70 mA 100 mA 0.
PAGE 873
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.2 Oscillator Characteristics 29.2.1 X1, XT1 oscillator characteristics (TA = −40 to +85°C, 1.6 V ≤ VDD ≤ 3.6 V, VSS = 0 V) Parameter X1 clock oscillation Resonator Ceramic resonator/crystal resonator Note frequency (fX) XT1 clock oscillation Conditions MIN. TYP. MAX. Unit MHz 2.7 V ≤ VDD ≤ 3.6 V 1.0 20.0 2.4 V ≤ VDD < 2.7 V 1.0 16.0 MHz 1.8 V ≤ VDD < 2.4 V 1.0 8.0 MHz 1.6 V ≤ VDD < 1.8 V 1.0 4.
PAGE 874
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.3 DC Characteristics 29.3.1 Pin characteristics (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output current, Note 1 high Conditions IOH1 Notes 1. TYP. MAX. −10.0 Unit Per pin for P00 to P06, P10 to P16, P30, P31, P40 to P43, P50, P51, P70 to P77, P120, P130, P140, P141 1.6 V ≤ EVDD0 ≤ 3.
PAGE 875
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output current, Note 1 low IOL1 Conditions MIN. Unit 20.0 Note 2 mA Per pin for P60 to P63 15.0 Note 2 mA Total of P05, P06, P10 to P16, P30, P31, P50, P51, P60 to P63, P70 to P77 Note 3 ) (When duty ≤ 70% 2.7 V ≤ EVDD0 ≤ 3.6 V 15.0 mA 1.8 V ≤ EVDD0 < 2.7 V 9.0 mA 1.6 V ≤ EVDD0 < 1.8 V 4.5 mA 2.
PAGE 876
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Input voltage, Symbol VIH1 Conditions P00 to P06, P10 to P16, P30, P31, MIN. Normal input buffer (3/5) TYP. MAX. Unit 0.8EVDD0 EVDD0 V 2.0 EVDD0 V 1.5 EVDD0 V P40 to P43, P50, P51, P70 to P77, high P120, P140, P141 VIH2 P01, P03, P04, P10, P11, TTL input buffer P13 to P16, P43 3.3 V ≤ EVDD0 ≤ 3.6 V TTL input buffer 1.
PAGE 877
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output voltage, VOH1 high Conditions MIN. P00 to P06, P10 to P16, P30, P31, 2.7 V ≤ EVDD0 ≤ 3.6 V, P40 to P43, P50, P51, P70 to P77, IOH1 = −2.0 mA P120, P130, P140, P141 1.8 V ≤ EVDD0 ≤ 3.6 V, IOH1 = −1.5 mA 1.6 V ≤ EVDD0 ≤ 3.6 V, IOH1 = −1.0 mA VOH2 P20 to P27, P150 to P154 1.6 V ≤ AVDD ≤ 3.
PAGE 878
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Input leakage ILIH1 Conditions P00 to P06, P10 to P16, P30, MIN. (5/5) TYP. MAX.
PAGE 879
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.3.2 Supply current characteristics (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Supply Note 1 current Symbol IDD1 (1/3) Conditions Operating mode HS (high-speed Note 5 main) mode MIN. Note 3 fIH = 32 MHz 2.1 Normal operation VDD = 3.0 V 4.6 7.0 mA Note 3 Normal operation VDD = 3.0 V 3.7 5.5 mA Note 3 Normal operation VDD = 3.0 V 2.7 4.0 mA Normal operation VDD = 3.0 V 1.2 1.
PAGE 880
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, on-chip pullup/pull-down resistors, and data flash rewriting. 2.
PAGE 881
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Note 2 Supply current Symbol IDD2 Note 1 Conditions HALT HS (high-speed mode main) mode MIN. Note 4 Note 4 Note 4 fIH = 32 MHz fIH = 24 MHz LS (low-speed main) mode Note 4 fIH = 8 MHz Note 4 fIH = 4 MHz Note 7 Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 fMX = 10 MHz , VDD = 3.
PAGE 882
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, on-chip pullup/pull-down resistors, and data flash rewriting. 2.
PAGE 883
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Low-speed on-chip Symbol (3/3) Conditions MIN. Note 1 IFIL TYP. MAX. Unit 0.20 μA 0.02 μA 0.02 μA μA oscillator operating current RTC operating IRTC Notes 1, 2, 3 current 12-bit interval timer IIT Notes 1, 2, 4 operating current Watchdog timer Notes 1, 2, 5 fIL = 15 kHz 0.22 Notes 6, 7 AVDD = 3.
PAGE 884
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A Notes 1. Current flowing to VDD. 2. When high-speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator). The supply current of the RL78 microcontrollers is the sum of the values of either IDD1 or IDD2, and IRTC, when the real-time clock operates in operation mode or HALT mode.
PAGE 885
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.4 AC Characteristics (TA = −40 to +85°C, AVDD ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Instruction cycle (minimum instruction execution time) Symbol TCY Conditions Main system clock (fMAIN) operation tEXH, tEXL 0.03125 1 μs 0.0625 1 μs LS (low-speed main) mode 1.8 V ≤ VDD ≤ 3.6 V 0.125 1 μs LV (low-voltage main) mode 1.6 V ≤ VDD ≤ 3.6 V 0.25 1 μs 1.8 V ≤ VDD ≤ 3.6 V 28.5 31.
PAGE 886
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A Note The following conditions are required for low-voltage interface when EVDD0 < VDD. 1.8 V ≤ EVDD0 < 2.7 V : MIN. 125 ns 1.6 V ≤ EVDD0 < 1.8 V : MIN. 250 ns Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer clock select register 0 (TPS0) and timer mode register 0n (TMR0n).
PAGE 887
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A TCY vs VDD (LS (low-speed main) mode) 10 When the high-speed on-chip oscillator clock is selected Cycle time TCY [μs] 1.0 During self programming When high-speed system clock is selected 0.125 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 3.6 5.0 5.5 6.0 Supply voltage VDD [V] TCY vs VDD (LV (low-voltage main) mode) Cycle time TCY [μs] 10 1.
PAGE 888
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH 0.7 VDD MIN. 0.3 VDD MAX. EXCLK TI/TO Timing tTIH tTIL TI00, TI01, TI03 to TI07 1/fTO TO00, TO01, TO03 to TO07 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR9 R01UH0305EJ0200 Rev.2.
PAGE 889
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A RESET Input Timing tRSL RESET R01UH0305EJ0200 Rev.2.
PAGE 890
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 29.5.1 Serial array unit (1) During communication at same potential (UART mode) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. Note 4 Transfer rate 2.4 V ≤ EVDD ≤ 3.6 V Theoretical value of the Note 1 LS MAX. fMCK/6 5.3 MIN. Note 2 LV MAX. MIN.
PAGE 891
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A UART mode connection diagram (during communication at same potential) Rx TxDq User device RL78 microcontroller Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1. 2.
PAGE 892
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SCKp cycle time tKCY1 2.7 V ≤ EVDD ≤ 3.6 V SCKp high-/low-level width tKH1, 2.7 V ≤ EVDD ≤ 3.6 V tKCY1 ≥ 2/fCLK Note 4 Note 4 SIp hold time (from SCKp↑) Delay time from SCKp↓ to SOp output MAX.
PAGE 893
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (3) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SCKp cycle time tKCY2 tKH2, width tKL2 SIp hold time tKSI2 Note 4 250 500 1000 ns 1.8 V ≤ EVDD0 ≤ 3.6 V tKCY1 ≥ 4/fCLK 500 500 1000 ns 1.7 V ≤ EVDD0 ≤ 3.6 V tKCY1 ≥ 4/fCLK 1000 1000 1000 ns 2.7 V ≤ EVDD0 ≤ 3.
PAGE 894
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SCKp cycle time Note 4 SCKp high-/low-level width SIp setup time Note 5 (to SCKp↑) SIp hold time Note 5 (from SCKp↑) Delay time from SCKp↓ Note 6 to SOp output tKCY2 tKH2, tKL2 tSIK2 tKSI2 tKSO2 2.7 V ≤ EVDD0 ≤ 3.
PAGE 895
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A Notes 1. HS is condition of HS (high-speed main) mode. 2. LS is condition of LS (low-speed main) mode. 3. LV is condition of LV (low-voltage main) mode. 4. Transfer rate in the SNOOZE mode: MAX. 1 Mbps 5. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time or SIp hold time becomes “from SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 6. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
PAGE 896
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO SOp SI User device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
PAGE 897
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 2 (5) During communication at same potential (simplified I C mode) (1/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SCLr clock frequency fSCL 2.7 V ≤ EVDD0 ≤ 3.6 V, Note 1 LS MAX. MIN. Note 4 1000 Note 2 LV MAX. MIN. Note 3 Unit MAX. 400 Note 4 400 Note 4 kHz Cb = 50 pF, Rb = 2.7 kΩ 1.8 V ≤ EVDD0 ≤ 3.
PAGE 898
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 2 (5) During communication at same potential (simplified I C mode) (2/2) (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Data hold time (transmission) tHD:DAT Conditions HS Note 1 LS Note 2 LV Note 3 Unit MIN. MAX. MIN. MAX. MIN. MAX. 2.7 V ≤ EVDD0 ≤ 3.6 V, Cb = 50 pF, Rb = 2.7 kΩ 0 305 0 305 0 305 ns 1.8 V ≤ EVDD0 ≤ 3.6 V, Cb = 100 pF, Rb = 3 kΩ 0 355 0 355 0 355 ns 1.
PAGE 899
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS Note 1 LS Note 2 LV Note 3 Unit MIN. MAX. MIN. MAX. MIN. MAX. Transfer rate Reception 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V Note 4 fMCK/6 fMCK/6 fMCK/6 bps 5.3 1.3 0.
PAGE 900
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (6) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS Note 1 LS Note 2 LV Note 3 Unit MIN. MAX. MIN. MAX. MIN. MAX. Transfer Transmission 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V rate Note 4 Note 4 Note 4 bps Mbps Theoretical value of the 1.2 1.2 1.
PAGE 901
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq User device RL78 microcontroller Tx RxDq UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1.
PAGE 902
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (7) Communication at different potential (2.5 V) (CSI mode) (master mode, SCKp... internal clock output, corresponding CSI00 only) (TA = −40 to +85°C, 2.7 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SCKp cycle time tKCY1 2.7 V ≤ EVDD0 ≤ 3.6 V, tKCY1 ≥ 2/fCLK Note 1 LS MAX. 300 Note 2 MIN. LV MAX. Note 3 MIN. Unit MAX. 1150 1150 ns tKCY1/2 − tKCY1/2 − ns 120 120 2.3 V ≤ Vb ≤ 2.
PAGE 903
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (8) Communication at different potential (1.8V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS Note 1 MIN. SCKp cycle time tKCY1 2.7 V ≤ EVDD0 ≤ 3.6 V, MAX. LS Note 2 MIN. MAX. LV Note 3 MIN. Unit MAX.
PAGE 904
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (8) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SIp setup time Note 4 (to SCKp↑) SIp hold time Note 4 (from SCKp↑) tSIK1 tKSI1 SIp hold time Note 5 (from SCKp↓) tSIK1 tKSI1 MAX. LV MIN. Note 3 Unit MAX. 479 479 ns 1.8 V ≤ EVDD0 < 3.3 V, 1.
PAGE 905
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A CSI mode connection diagram (during communication at different potential) Vb Rb SCKp RL78 microcontroller Remarks 1. Vb Rb SCK SIp SO SOp SI User device Rb[Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb[F]: Communication line (SCKp, SOp) load capacitance, Vb[V]: Communication line voltage 2.
PAGE 906
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY1 t KL1 t KH1 SCKp t SIK1 SIp t KSI1 Input data t KSO1 Output data SOp CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
PAGE 907
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (9) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SCKp cycle time Note 4 tKCY2 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V tKH2, tKL2 tSIK2 tKSI2 Delay time from SCKp↓ Note 7 to SOp output tKSO2 MAX. LV MIN. Note 3 Unit MAX.
PAGE 908
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A CSI mode connection diagram (during communication at different potential) Vb Rb SCKp RL78 microcontroller Remarks 1. SCK SIp SO SOp SI User device Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2. p: CSI number (p = 00, 10, 20), m: Unit number (m = 0, 1), n: Channel number (n = 00, 02, 10), g: PIM and POM number (g = 0, 1) 3.
PAGE 909
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY2 t KL2 t KH2 SCKp t SIK2 SIp t KSI2 Input data t KSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
PAGE 910
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 2 (10) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (1/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. SCLr clock frequency fSCL 2.7 V ≤ EVDD0 ≤ 3.6 V, Note 1 LS MAX. MIN. LV MAX. MIN. Note 3 Unit MAX. 300 Note 4 300 Note 4 300 Note 4 300 Note 4 300 Note 4 300 1000 Note 4 Note 2 Note 4 kHz Note 4 kHz Note 4 kHz 2.
PAGE 911
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 2 (10) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (2/2) (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions HS MIN. Data setup time (reception) Data hold time (transmission) tSU:DAT tHD:DAT Note 1 LS MAX. MIN. Note 2 MAX. LV MIN. Note 3 Unit MAX. 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.
PAGE 912
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 2 Simplified I C mode connection diagram (during communication at different potential) Vb Rb Vb Rb SDA SDAr RL78 microcontroller User device SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD : DAT Remarks 1.
PAGE 913
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.5.2 Serial interface IICA 2 (1) I C standard mode (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.
PAGE 914
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (2) I2C fast mode, fast mode plus (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Note 7 Conditions Fast Mode Fast Mode Unit Note 8 Plus HS SCLA0 clock frequency Setup time of restart Note 5 Hold time when SCLA0 MAX. MIN. 2.7 V ≤ EVDD0 ≤ 3.6 V 0 400 0 400 0 400 0 1000 1.8 V ≤ EVDD0 ≤ 3.6 V 0 400 0 400 0 400 − tSU:STA 2.7 V ≤ EVDD0 ≤ 3.6 V 0.6 0.6 0.6 1.
PAGE 915
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A IICA serial transfer timing tLOW SCL0 tHD:DAT tHD:STA tHIGH tSU:STA tHD:STA tSU:STO tSU:DAT SDA0 tBUF Stop condition Start condition R01UH0305EJ0200 Rev.2.
PAGE 916
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.6 Analog Characteristics 29.6.1 A/D converter characteristics Division of A/D Converter Characteristics Reference voltag Reference voltage (+) = AVREFP Reference voltage (+) = AVDD Reference voltage (−) = AVREFM Reference voltage (−) = AVSS Reference voltage (+) = Internal refrence voltage Reference voltage (−) = AVSS Input channel High-accuracy channel; ANI0 to See 29.6.1 (1) ANI12 See 29.6.1 (2) See 29.6.1 (6) See 29.6.
PAGE 917
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (2) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI2 to ANI12 (TA = −40 to +85°C, 1.6 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (−) = AVREFM = 0 V) Parameter Symbol Resolution Conditions 2.4 V ≤ AVREFP ≤ AVDD ≤ 3.6 V RES 1.8 V ≤ AVREFP ≤ AVDD ≤ 3.6 V MIN. 8 1.
PAGE 918
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (3) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM = 0), target for conversion: ANI0 to ANI12 (TA = −40 to +85°C, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (−) = AVSS = 0 V) Parameter Symbol Resolution Conditions 2.4 V ≤ AVDD ≤ 3.6 V RES 1.8 V ≤ AVDD ≤ 3.6 V MIN. 8 Overall error AINL Conversion time tCONV MAX.
PAGE 919
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (4) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI16 to ANI30, interanal reference voltage, temperature sensor output voltage (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, 1.6 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.
PAGE 920
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (5) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM = 0), target for conversion: ANI16 to ANI30, interanal reference voltage, temperature sensor output voltage (TA = −40 to +85°C, 1.6 V ≤ EVDD0 ≤ VDD0 ≤ 3.6 V, 1.6 V ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (−) = AVSS = 0 V) Parameter Symbol Resolution Conditions 2.
PAGE 921
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A (6) When reference voltage (+) = Internal reference voltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM = 0), target ANI pin: ANI0 to ANI12, ANI16 to ANI30 (TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 3.6 V, 1.6 V ≤ EVDD ≤ VDD, 1.
PAGE 922
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V) Parameter Detection Supply voltage level Symbol VLVD2 voltage VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 MIN. TYP. MAX. Unit Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.
PAGE 923
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A LVD Detection Voltage of Interrupt & Reset Mode (TA = −40 to +85°C, VPDR ≤ VDD ≤ 3.
PAGE 924
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Data retention supply voltage Conditions MIN. VDDDR 1.46 TYP. Note MAX. Unit 3.6 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.
PAGE 925
CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) RL78/G1A 29.10 Timing Specs for Switching Flash Memory Programming Modes (TA = −40 to +85°C, 1.8 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol How long from when an external reset Conditions MIN. TYP. POR and LVD reset must end before the tSUINIT MAX. Unit 100 ms external reset ends.
PAGE 926
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) This chapter describes the following electrical specifications. Target products G: Industrial applications TA = −40 to +105°C R5F10EBAGNA, R5F10EBCGNA, R5F10EBDGNA, R5F10EBEGNA R5F10EGAGFB, R5F10EGCGFB, R5F10EGDGFB, R5F10EGEGFB R5F10EGAGNA, R5F10EGCGNA, R5F10EGDGNA, R5F10EGEGNA R5F10ELCGFB, R5F10ELDGFB, R5F10ELEGFB Cautions 1.
PAGE 927
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25°C) (1/2) Parameter Supply voltage Symbols Conditions Ratings Unit VDD −0.5 to +6.5 V EVDD0 −0.5 to +6.5 V AVDD −0.5 to +4.6 V −0.3 to AVDD +0.3 Note 3 AVREFP EVSS0 −0.5 to +0.3 AVSS −0.5 to +0.3 V V −0.3 to AVDD +0.3 AVREFM V Note 3 V and AVREFM ≤ AVREFP REGC pin input voltage VIREGC REGC −0.3 to +2.8 V and −0.
PAGE 928
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Output current, high Symbols IOH1 Conditions Per pin P00 to P06, P10 to P16, P30, P31, Ratings Unit −40 mA −70 mA −100 mA −0.1 mA −1.3 mA 40 mA 70 mA 100 mA 0.
PAGE 929
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.2 Oscillator Characteristics 30.2.1 X1, XT1 oscillator characteristics (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, VSS = 0 V) Parameter Resonator X1 clock oscillation Ceramic resonator/crystal resonator Note frequency (fX) XT1 clock oscillation Conditions MIN. 2.7 V ≤ VDD ≤ 3.6 V 1.0 2.4 V ≤ VDD < 2.7 V 1.0 Crystal resonator TYP. MAX. Unit 20.0 MHz 16.0 32 32.
PAGE 930
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.3 DC Characteristics 30.3.1 Pin characteristics (TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output current, Note 1 high Conditions IOH1 IOH2 Notes 1. MIN. (1/5) TYP. MAX. −3.0 Unit Per pin for P00 to P06, P10 to P16, P30, P31, P40 to P43, P50, P51, P70 to P77, P120, P130, P140, P141 2.4 V ≤ EVDD0 ≤ 3.
PAGE 931
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output current, Note 1 low IOL1 Conditions MIN. Note 2 8.5 Per pin for P60 to P63 15.0 Total of P05, P06, P10 to P16, P30, P31, P50, P51, P60 to P63, P70 to P77 Note 3 ) (When duty ≤ 70% mA mA 15.0 mA 2.4 V ≤ EVDD0 < 2.7 V 9.0 mA 2.7 V ≤ EVDD0 ≤ 3.6 V 35.0 mA 2.4 V ≤ EVDD0 < 2.
PAGE 932
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Input voltage, Symbol VIH1 Conditions P00 to P06, P10 to P16, P30, P31, MIN. Normal input buffer TYP. (3/5) MAX. Unit 0.8EVDD0 EVDD0 V 2.0 EVDD0 V 1.5 EVDD0 V P40 to P43, P50, P51, P70 to P77, high P120, P140, P141 VIH2 P01, P03, P04, P10, P11, TTL input buffer P13 to P16, P43 3.
PAGE 933
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Output voltage, VOH1 high Conditions MIN. P00 to P06, P10 to P16, P30, P31, 2.7 V ≤ EVDD0 ≤ 3.6 V, P40 to P43, P50, P51, P70 to P77, IOH1 = −2.0 mA P120, P130, P140, P141 2.4 V ≤ EVDD0 ≤ 3.6 V, IOH1 = −1.5 mA VOH2 P20 to P27, P150 to P154 2.4 V ≤ AVDD ≤ 3.
PAGE 934
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Items Symbol Input leakage ILIH1 Conditions P00 to P06, P10 to P16, P30, MIN. TYP. (5/5) MAX.
PAGE 935
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.3.2 Supply current characteristics (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Supply current Symbol Note 1 IDD1 (1/3) Conditions Operating mode HS (high-speed Note 5 main) mode MIN. Note 3 fIH = 32 MHz Unit VDD = 3.0 V 2.1 Normal operation VDD = 3.0 V 4.6 7.5 mA Note 3 Normal operation VDD = 3.0 V 3.7 5.8 mA Note 3 Normal operation VDD = 3.0 V 2.
PAGE 936
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, on-chip pullup/pull-down resistors, and data flash rewriting. 2.
PAGE 937
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Note 2 Supply current Symbol IDD2 Note 1 Conditions HALT HS (high-speed mode main) mode Note 4 Note 4 Note 4 MIN. fIH = 32 MHz fIH = 24 MHz HS (high-speed main) mode Note 7 Note 3 fMX = 20 MHz , VDD = 3.0 V Note 3 fMX = 10 MHz , VDD = 3.0 V VDD = 3.0 V 0.54 2.90 mA VDD = 3.0 V 0.44 2.30 mA VDD = 3.0 V 0.
PAGE 938
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A Notes 1. Total current flowing into VDD and EVDD0, including the input leakage current flowing when the level of the input pin is fixed to VDD, EVDD0 or VSS, EVSS0. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, on-chip pullup/pull-down resistors, and data flash rewriting. 2.
PAGE 939
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Low-speed on-chip Symbol (3/3) Conditions MIN. Note 1 IFIL TYP. MAX. Unit 0.20 μA 0.02 μA 0.02 μA μA oscillator operating current RTC operating IRTC Notes 1, 2, 3 current 12-bit interval timer IIT Notes 1, 2, 4 operating current Watchdog timer Notes 1, 2, 5 fIL = 15 kHz 0.22 Notes 6, 7 AVDD = 3.
PAGE 940
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Notes 1. Current flowing to VDD. 2. When high-speed on-chip oscillator and high-speed system clock are stopped. 3. Current flowing only to the real-time clock (RTC) (excluding the operating current of the low-speed on-chip ocsillator and the XT1 oscillator).
PAGE 941
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.4 AC Characteristics (TA = −40 to +105°C, AVDD ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.
PAGE 942
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) Minimum Instruction Execution Time during Main System Clock Operation TCY vs VDD (HS (high-speed main) mode) 10 1.0 Cycle time TCY [μs] When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.1 0.0625 0.05 0.03125 0.01 0 1.0 2.0 3.0 4.0 2.4 2.7 3.6 5.0 6.0 Supply voltage VDD [V] R01UH0305EJ0200 Rev.2.
PAGE 943
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL External System Clock Timing 1/fEX tEXL tEXH 0.7 VDD MIN. 0.3 VDD MAX. EXCLK TI/TO Timing tTIH tTIL TI00, TI01, TI03 to TI07 1/fTO TO00, TO01, TO03 to TO07 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP11 Key Interrupt Input Timing tKR KR0 to KR9 R01UH0305EJ0200 Rev.2.
PAGE 944
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RESET Input Timing tRSL RESET R01UH0305EJ0200 Rev.2.
PAGE 945
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.5 Peripheral Functions Characteristics AC Timing Test Points VIH/VOH VIH/VOH Test points VIL/VOL VIL/VOL 30.5.1 Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Conditions MIN. TYP. Note 1 Transfer rate Theoretical value of the MAX.
PAGE 946
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol SCKp cycle time tKCY1 SCKp high-/low-level width Note 1 SIp setup time (to SCKp↑) Note 1 SIp hold time (from SCKp↑) Delay time from SCKp↓ to SOp output Conditions MIN. TYP. MAX. Unit 2.7 V ≤ EVDD0 ≤ 3.
PAGE 947
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCKp cycle time Note 1 Symbol tKCY2 Conditions 2.7 V ≤ EVDD0 ≤ 3.6 V MIN. TYP. MAX. Unit 16 MHz < fMCK 16/fMCK ns fMCK ≤ 16 MHz 12/fMCK ns 12/fMCK and ns 2.4 V ≤ EVDD0 ≤ 3.
PAGE 948
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode connection diagram (during communication at same potential) SCK SCKp RL78 microcontroller SIp SO SOp SI User device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
PAGE 949
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 (4) During communication at same potential (simplified I C mode) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 2.7 V ≤ EVDD0 ≤ 3.6 V, MAX. Unit 400 Note 1 kHz 100 Note 1 kHz Cb = 50 pF, Rb = 2.7 kΩ 2.4 V ≤ EVDD0 ≤ 3.6 V, Cb = 100 pF, Rb = 3 kΩ Hold time when SCLr = “L” tLOW 2.7 V ≤ EVDD0 ≤ 3.
PAGE 950
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 Simplified I C mode mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78 microcontroller User device SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at same potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD : DAT Remarks 1. 2. 3.
PAGE 951
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (5) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Note 1 Transfer rate Conditions Reception MIN. 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V Theoretical value of the TYP. MAX. Unit fMCK/12 bps 2.
PAGE 952
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (5) Communication at different potential (1.8 V, 2.5 V) (UART mode) (dedicated baud rate generator output) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Transfer Symbol Conditions Transmission TYP. 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V rate MIN. Theoretical value of the maximum MAX. Unit Note 1 bps 1.2 Note 2 Mbps transfer rate Cb = 50 pF, Rb = 2.
PAGE 953
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq User device RL78 microcontroller Tx RxDq UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1.
PAGE 954
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (6) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCKp cycle time Symbol tKCY1 Conditions 2.7 V ≤ EVDD0 ≤ 3.6 V, MIN. TYP. MAX. Unit tKCY1 ≥ 4/fCLK 1000 ns tKCY1 ≥ 4/fCLK 2300 ns tKCY1/2 − 340 ns tKCY1/2 − 916 ns tKCY1/2 − 36 ns tKCY1/2 − 100 ns 2.
PAGE 955
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (6) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.
PAGE 956
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY1 t KL1 t KH1 SCKp t SIK1 SIp t KSI1 Input data t KSO1 Output data SOp CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
PAGE 957
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (7) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCKp cycle time Note 1 SCKp high-/low-level width Symbol tKCY2 tKH2, tKL2 Conditions MIN. TYP. MAX. Unit 2.7 V ≤ EVDD0 ≤ 3.6 V, 24 MHz < fMCK 40/fMCK ns 2.3 V ≤ Vb ≤ 2.
PAGE 958
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode connection diagram (during communication at different potential) Vb Rb SCKp RL78 microcontroller Remarks 1. SCK SIp SO SOp SI User device Rb[Ω]: Communication line (SOp) pull-up resistance, Cb[F]: Communication line (SOp) load capacitance, Vb[V]: Communication line voltage 2.
PAGE 959
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) t KCY2 t KL2 t KH2 SCKp t SIK2 SIp t KSI2 Input data t KSO2 Output data SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
PAGE 960
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 (8) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (1/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 2.7 V ≤ EVDD0 ≤ 3.6 V, MAX. 400 Unit Note 1 kHz Note 1 kHz Note 1 kHz 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 2.7 V ≤ EVDD0 ≤ 3.6 V, 100 2.3 V ≤ Vb ≤ 2.7 V, Cb = 100 pF, Rb = 2.
PAGE 961
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 (8) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) (2/2) (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Data setup time (reception) Data hold time (transmission) Symbol tSU:DAT tHD:DAT Conditions MIN. MAX. Unit 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.7 V, Cb = 50 pF, Rb = 2.7 kΩ 1/fMCK + Note 2 340 ns 2.7 V ≤ EVDD0 ≤ 3.6 V, 2.3 V ≤ Vb ≤ 2.
PAGE 962
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 2 Simplified I C mode connection diagram (during communication at different potential) Vb Rb Vb Rb SDA SDAr RL78 microcontroller User device SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/fSCL tLOW tHIGH SCLr SDAr tHD : DAT Remarks 1.
PAGE 963
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.5.2 Serial interface IICA 2 (1) I C standard mode, fast mode (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol Standard Conditions Fast Mode Unit Mode MIN. SCLA0 clock frequency fSCL Fast mode: fCLK ≥ 3.5 MHz 2.4 V ≤ EVDD0 ≤ 3.6 V Normal mode: fCLK ≥ 1 MHz 2.4 V ≤ EVDD0 ≤ 3.6 V 0 MAX. MIN. MAX. 0 400 100 kHz kHz tSU:STA 4.7 0.6 μs tHD:STA 4.0 0.
PAGE 964
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.6 Analog Characteristics 30.6.1 A/D converter characteristics Division of A/D Converter Characteristics Reference voltag Reference voltage (+) = AVREFP Reference voltage (+) = AVDD Reference voltage (−) = AVREFM Reference voltage (−) = AVSS Reference voltage (+) = Internal refrence voltage Reference voltage (−) = AVSS Input channel High-accuracy channel; ANI0 to See 30.6.1 (1) See 30.6.1 (2) See 30.6.
PAGE 965
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (2) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM = 0), target for conversion: ANI0 to ANI12 (TA = −40 to +105°C, 2.4 V ≤ AVDD ≤ VDD ≤ 3.6 V, VSS = 0 V, AVSS = 0 V, Reference voltage (+) = AVDD, Reference voltage (−) = AVSS = 0 V) Parameter Symbol Resolution Conditions 2.4 V ≤ AVDD ≤ 3.6 V RES Overall error AINL 12-bit resolution 2.4 V ≤ AVDD ≤ 3.
PAGE 966
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (3) When reference voltage (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage (−) = AVREFM/ANI1 (ADREFM = 1), target for conversion: ANI16 to ANI30, interanal reference voltage, temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, 2.4 V ≤ AVREFP ≤ AVDD ≤ VDD ≤ 3.
PAGE 967
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (4) When reference voltage (+) = AVDD (ADREFP1 = 0, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM = 0), target for conversion: ANI16 to ANI30, interanal reference voltage, temperature sensor output voltage (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD0 ≤ 3.6 V, 2.4 V ≤ AVDD ≤ VDD ≤ 3.
PAGE 968
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A (5) When reference voltage (+) = Internal reference voltage (1.45 V) (ADREFP1 = 1, ADREFP0 = 0), reference voltage (−) = AVSS (ADREFM = 0), target for conversion: ANI0 to ANI12, ANI16 to ANI30 (TA = −40 to +105°C, 2.4 V ≤ VDD ≤ 3.6 V, 2.4 V ≤ EVDD ≤ VDD, 2.
PAGE 969
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) RL78/G1A 30.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = −40 to +105°C, VPDR ≤ VDD ≤ 3.6 V, VSS = 0 V) Parameter Detection Symbol Supply voltage level VLVD2 voltage VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Minimum pulse width Conditions MIN. TYP. MAX. Unit Power supply rise time 3.01 3.13 3.25 V Power supply fall time 2.94 3.06 3.18 V Power supply rise time 2.
PAGE 970
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +105°C, VSS = 0 V) Parameter Symbol Data retention supply voltage Conditions MIN. VDDDR 1.44 TYP. Note MAX. Unit 3.6 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is effected, but data is not retained when a POR reset is effected.
PAGE 971
RL78/G1A CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) 30.10 Timing Specs for Switching Flash Memory Programming Modes (TA = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V) Parameter Symbol How long from when an external reset Conditions MIN. TYP. POR and LVD reset must end before the tSUINIT MAX. Unit 100 ms external reset ends.
PAGE 972
RL78/G1A CHAPTER 31 PACKAGE DRAWINGS CHAPTER 31 PACKAGE DRAWINGS 31.1 25-pin Products R5F10E8AALA, R5F10E8CALA, R5F10E8DALA, R5F10E8EALA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-WFLGA25-3x3-0.50 PWLG0025KA-A P25FC-50-2N2-2 0.01 21x b w S A S AB M A ZD D x e ZE 5 4 B 3 2.27 E 2 C 1 E w S B INDEX MARK y1 S D C B A D 2.27 INDEX MARK A S (UNIT:mm) y S DETAIL OF C PART DETAIL OF D PART R0.17±0.05 0.43±0.05 R0.12±0.05 0.33±0.05 0.50±0.05 0.365±0.
PAGE 973
RL78/G1A CHAPTER 31 PACKAGE DRAWINGS 31.2 32-pin Products R5F10EBAANA, R5F10EBCANA, R5F10EBDANA, R5F10EBEANA R5F10EBAGNA, R5F10EBCGNA, R5F10EBDGNA, R5F10EBEGNA JEITA Package code P-HWQFN32-5x5-0.50 RENESAS code Previous code MASS(TYP.)[g] PWQN0032KB-A P32K8-50-3B4-5 0.06 D 17 24 DETAIL OF A PART 16 25 E A 9 32 A1 C2 8 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 1 8 9 32 Dimension in Millimeters Min Nom Max D 4.95 5.00 5.05 E 4.95 5.00 5.
PAGE 974
RL78/G1A CHAPTER 31 PACKAGE DRAWINGS 31.3 48-pin Products R5F10EGAAFB, R5F10EGCAFB, R5F10EGDAFB, R5F10EGEAFB R5F10EGAGFB, R5F10EGCGFB, R5F10EGDGFB, R5F10EGEGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP48-7x7-0.50 PLQP0048KF-A P48GA-50-8EU-1 0.16 HD D detail of lead end 36 25 37 A3 24 c θ E L Lp HE L1 (UNIT:mm) 13 48 12 1 ZE e ZD b x M S A ITEM D DIMENSIONS 7.00±0.20 E 7.00±0.20 HD 9.00±0.20 HE 9.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.
PAGE 975
RL78/G1A CHAPTER 31 PACKAGE DRAWINGS R5F10EGAANA, R5F10EGCANA, R5F10EGDANA, R5F10EGEANA R5F10EGAGNA, R5F10EGCGNA, R5F10EGDGNA, R5F10EGEGNA JEITA Package code P-HWQFN48-7x7-0.50 RENESAS code Previous code MASS(TYP.)[g] PWQN0040KB-A 48PJN-A P40K8-50-5B4-6 0.13 D 25 36 DETAIL OF A PART 24 37 E A A1 13 48 C2 12 1 INDEX AREA A S y S Referance Symbol D2 A Lp EXPOSED DIE PAD 12 1 13 48 Dimension in Millimeters Min Nom Max D 6.95 7.00 7.05 E 6.95 7.00 7.05 A 0.
PAGE 976
RL78/G1A CHAPTER 31 PACKAGE DRAWINGS 31.4 64-pin Products R5F10ELCAFB, R5F10ELDAFB, R5F10ELEAFB R5F10ELCGFB, R5F10ELDGFB, R5F10ELEGFB JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LFQFP64-10x10-0.50 PLQP0064KF-A P64GB-50-UEU-2 0.35 HD D detail of lead end 48 33 49 A3 32 c θ E L Lp HE L1 (UNIT:mm) 17 64 1 16 ZE e ZD b x M S ITEM D DIMENSIONS 10.00±0.20 E 10.00±0.20 HD 12.00±0.20 HE 12.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.
PAGE 977
RL78/G1A CHAPTER 31 PACKAGE DRAWINGS R5F10ELCABG, R5F10ELDABG, R5F10ELEABG JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-VFBGA64-4x4-0.40 PVBG0064LA-A P64F1-40-AA2-2 0.03 w D S A ZE ZD A 8 7 6 B 5 4 E 3 2 1 H G F E D C B A INDEX MARK w S B (UNIT:mm) A y1 A2 S S y e S b x M A1 S A B INDEX MARK ITEM D DIMENSIONS E 4.00±0.10 w 0.15 4.00±0.10 A 0.89±0.10 A1 0.20± 0.05 A2 0.69 e 0.40 b 0.25 ± 0.05 x 0.05 y 0.08 y1 0.20 ZD 0.60 ZE 0.
PAGE 978
RL78/G1A APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/11) Page Description Classification R01UH0305EJ0110 → R01UH0305EJ0200 CHAPTER 1 OUTLINE p.1 Modification of 1.1 Features (b) p.5 Modification of Table 1-1. List of Ordering Part Numbers (b) p.7 Modification of Remark 3 (b) p.17 Modification of 1.6 Outline of Functions (b) CHAPTER 2 PIN FUNCTIONS p.20, 21 Modification of 2.1.1 25-pin products (b) p.22, 23 Modification of 2.1.
PAGE 979
RL78/G1A APPENDIX A REVISION HISTORY (2/11) Page Description Classification p.110 Modification of 4.3.6 Port mode control registers (PMCxx) (c) p.111 Modification of 4.3.7 A/D port configuration register (ADPC) (c) p.112 Modification of 4.3.8 Peripheral I/O redirection register (PIOR) (c) p.113 Modification of 4.3.9 Global digital input disable register (GDIDIS) (c) p.114 Modification of 4.3.10 Global analog input disable register (GAIDIS) (c) p.116 Modification of 4.4.
PAGE 980
RL78/G1A APPENDIX A REVISION HISTORY (3/11) Page Description Classification p.198 Modification of 6.3.2 Timer clock select register m (TPSm) (c) p.199 Modification of Caution in Figure 6-10. Format of Timer Clock Select register m (TPSm) (c) p.215 Modification of Figure 6-21. Format of Input Switch Control Register (ISC) (c) p.216 Modification of 6.3.14 Noise filter enable register 1 (NFEN1) (c) p.218 Modification of 6.3.
PAGE 981
RL78/G1A APPENDIX A REVISION HISTORY (4/11) Page Description Classification p.306 Modification of 7.3.10 Month count register (MONTH) (c) p.309 Modification of 7.3.16 Port mode register 3 (PM3) (c) p.309 Modification of 7.3.17 Port register 3 (P3) (c) p.315 Modification of 7.4.5 1 Hz output of real-time clock (c) Modification of Correction example 1 in 7.4.6 Example of watch error correction of real- (c) p.317 time clock Modification of Figure 7-25.
PAGE 982
RL78/G1A APPENDIX A REVISION HISTORY (5/11) Page Description Classification p.393 Modification of Figure 11-37. Flowchart for Setting up SNOOZE Mode (c) p.396 Modification of 11.10 Cautions for A/D Converter (c) CHAPTER 12 SERIAL ARRAY UNIT p.405 Modification of Figure 12-1. Block Diagram of Serial Array Unit 0 (c) p.406 Modification of Figure 12-2. Block Diagram of Serial Array Unit 1 (c) p.407 Modification of 12.2.1 Shift register (c) p.408 Modification of Figure 12-3.
PAGE 983
RL78/G1A APPENDIX A REVISION HISTORY (6/11) Page Description Modification of Figure 12-41. Initial Setting Procedure for Master p.460 Classification (c) Transmission/Reception Modification of Figure 12-44. Timing Chart of Master Transmission/Reception (in Single- p.463 (c) Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) Modification of Figure 12-45. Flowchart of Master Transmission/Reception (in Single- p.464 (c) Transmission/Reception Mode) Modification of Figure 12-46.
PAGE 984
RL78/G1A APPENDIX A REVISION HISTORY (7/11) Page Description Modification of Figure 12-82. Flowchart of UART Transmission (in Continuous p.514 Classification (c) Transmission Mode) p.515 p.516 Modification of 12.6.2 UART reception (c) Modification of Note in Figure 12-83. Example of Contents of Registers for UART (c) Reception of UART (UART0 to UART2) (1/2) p.518 Modification of Figure 12-85. Procedure for Stopping UART Reception (c) p.520 Modification of Figure 12-87.
PAGE 985
RL78/G1A APPENDIX A REVISION HISTORY (8/11) Page Description Classification p.658 Modification of Figure 14-5. Format of Multiplication/Division Control Register (MDUC) (c) p.665 Modification of Figure 14-9. Timing Diagram of Multiply-Accumulation (signed) Operation (c) CHAPTER 15 DMA CONTROLLER p.668 Modification of 15.1 Functions of DMA Controller (c) p.681 Modification of Figure 15-9. Example of Setting for UART Consecutive Reception + ACK (c) Transmission p.
PAGE 986
RL78/G1A APPENDIX A REVISION HISTORY (9/11) Page Description Modification of Figure 18-5. When the Interrupt Request Signal is Generated in the p.739 Classification (c) SNOOZE Mod and Figure 18-6. When the Interrupt Request Signal is not Generated in the SNOOZE Mode CHAPTER 19 RESET FUNCTION p.740 Modification of CHAPTER 19 RESET FUNCTION (c) p.742, 743 Modification of figure, Note, and Caution in Figure 19-2. Timing of Reset by RESET Input (c) and Figure 19-3.
PAGE 987
RL78/G1A APPENDIX A REVISION HISTORY (10/11) Page Description Classification p.784 Modification of 22.3.7 Frequency detection function (c) p.785 Modification of 22.3.7.1 Timer input select register 0 (TIS0) (c) p.786 Modification of 22.3.8 A/D test function (c) p.787 Modification of Figure 22-15. Configuration of A/D Test Function (c) p.788 Modification of 22.3.8.1 A/D test register (ADTES) (c) CHAPTER 24 OPTION BYTE p.792, 793 Modification of 24.1.
PAGE 988
RL78/G1A APPENDIX A REVISION HISTORY (11/11) Page Description Classification p.868 Modification of AC Timing Test Points and TI/TO Timing (c) p.870 Modification of AC Timing Test Points in 29.5 Peripheral Functions Characteristics (c) p. 879, 880, 882 to Modification of Caution (c) p.896 to 901 Modification of 29.6.1 A/D converter characteristics (c) p.904 Modification of 29.7 Data Memory STOP Mode Low Supply Voltage Data Retention (c) 884, 887, 891 Characteristics p.
PAGE 989
RL78/G1A APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/5) Page Description Classification R01UH0305EJ0100 → R01UH0305EJ0110 CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = −40 to +105°C) (TARGET) p.952 Modification of ISNOZ and note 7 in 30.3.2 Supply current characteristics (c) R01UH0305EJ0003 → R01UH0305EJ0100 CHAPTER 1 OUTLINE p.
PAGE 990
RL78/G1A APPENDIX A REVISION HISTORY (2/5) Page CHAPTER 5 Description Classification CLOCK GENERATOR p.162 Addition of description to 5.1 (1) <2> High-speed on-chip oscillator (c) p.165 Modification of Figure 5-1. Block Diagram of Clock Generator (c) Modification of caution 3 in Figure 5-2. Format of Clock Operation Mode Control Register (c) p.167 (CMC) p.185 Modification of description in 5.4.3 High-speed on-chip oscillator (c) p.187 Modification of Figure 5-14.
PAGE 991
RL78/G1A APPENDIX A REVISION HISTORY (3/5) Page Description Classification CHAPTER 11 A/D CONVERTER p.361 Modification of Figure 11-1. Block Diagram of A/D Converter (c) p.365 Modification of caution 1 in Figure 11-2. Format of Peripheral Enable Register 0 (PER0) (c) p.367 Modification of Table 11-1. Settings of ADCS and ADCE Bits (c) p.378 Modification of caution 1 in Figure 11-6. Format of A/D Converter Mode Register 1 (ADM1) (c) p.379, 380 Modification of caution in Figure 11-7.
PAGE 992
RL78/G1A APPENDIX A REVISION HISTORY (4/5) Page Description Classification CHAPTER 18 STANDBY FUNCTION p.758 Modification of Table 18-1. Operating Statuses in HALT Mode (c) p.760, 761 Modification of figure and note in Figure 18-4. HALT Mode Release by Reset (c) p.762 Modification of caution 1 in 18.3.2 (1) STOP mode setting and operating statuses (c) p.764 Deletion of caution 1 in Table 18-2. Operating Statuses in STOP Mode (c) p.
PAGE 993
RL78/G1A APPENDIX A REVISION HISTORY (5/5) Page Description Classification CHAPTER 28 INSTRUCTION SET p.880 Modification of Table 28-5. Operation List (c) CHAPTER 29 ELECTRICAL SPECIFICATIONS (TA = −40 to +85°C) Though out Deletion of target in ELECTRICAL SPECIFICATIONS (b) p.884 Addition of target products (d) p.885 Modification of description and addition of remark 3 to 29.1 Absolute Maximum Ratings (c) p.887 Modification of description and note in 29.2.
PAGE 994
RL78/G1A APPENDIX A REVISION HISTORY (1/8) Edition Rev.0.03 Description Renamed interval timer (unit) to 12-bit interval timer Chapter Though out Renamed VLVI, VLVIH, VLVIL to VLVD, VLVDH, VLVDL (LVD detection voltage) Renamed interrupt source of RAM parity error (RAMTOP) to RPE Modification of 1.2 Ordering Information CHAPTER 1 OUTLINE Addition of Figure 1-1. Part Number, Memory Size, and Package of RL78/G1A Modification of 1.5.1 25-pin products to 1.5.4 64-pin products Modification of Table 2-1.
PAGE 995
RL78/G1A APPENDIX A REVISION HISTORY (2/8) Edition Rev.0.03 Description Chapter Addition of remark to 4.3.9 Global digital input disable register (GDIDIS) CHAPTER 4 PORT Modification of description to 4.3.10 Global analog input disable register (GAIDIS) FUNCTIONS Modification of description in 4.4.1 (2) Input mode and 4.4.3 (2) Input mode Addition of description to 4.4.4 (2) Setting procedure when using I/O pins of IIC00, IIC10, and IIC20 functions Addition of caution to 4.
PAGE 996
RL78/G1A APPENDIX A REVISION HISTORY (3/8) Edition Rev.0.03 Description Chapter Modification of remark 1 in Figure 6-31. Operation Timing (In Capture & One-count CHAPTER 6 TIMER Mode : High-level Width Measurement) ARRAY UNIT Modification of description in 6.6.
PAGE 997
RL78/G1A APPENDIX A REVISION HISTORY (4/8) Edition Rev.0.03 Description Chapter Addition of note 1 to 12.1.1 3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CHAPTER 12 SERIAL CSI21) ARRAY UNIT Addition of note to 12.1.2 UART (UART0 to UART2) Modification of Figures 12-1 and 12-2 block diagram of the serial array unit 0, 1 Modification of description in 12.2.2 Lower 8/9 bits of the serial data register mn (SDRmn) Modification of caution 1 in Figure 12-5.
PAGE 998
RL78/G1A APPENDIX A REVISION HISTORY (5/8) Edition Rev.0.03 Description Chapter Modification of note 1 and caution 1 in Figure 12-94. Timing Chart of SNOOZE Mode CHAPTER 12 SERIAL Operation (Abnormal Operation <2>) ARRAY UNIT Modification of description in Table 12-3. Selection of Operation Clock For UART Modification of description and note in 12.7.1 LIN transmission and 12.7.2 LIN reception Modification of Figure 12-99. Master Transmission Operation of LIN Modification of Figure 12-100.
PAGE 999
RL78/G1A APPENDIX A REVISION HISTORY (6/8) Edition Rev.0.03 Description Chapter Deletion of caution 2 in Figure 16-2. Format of Interrupt Request Flag Registers CHAPTER 16 (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (128-pin) INTERRUPT FUNCTION Modification of value and addition of note in Table 16-4. Time from Generation of Maskable Interrupt Until Servicing Modification of Figure 16-8. Interrupt Request Acknowledgment Timing (Minimum Time) and Figure 16-9.
PAGE 1000
RL78/G1A APPENDIX A REVISION HISTORY (7/8) Edition Rev.0.03 Description Chapter Modification of Figure 22-6. CRC Operation Function (General-Purpose CRC) CHAPTER 22 SAFETY Modification of caution in Figure 22-7. Format of RAM Parity Error Control Register FUNCTIONS (RPECTL) Addition of remark to Figure 22-11. Format of Invalid Memory Access Detection Control Register (IAWCTL) Addition of description to 22.3.8 A/D test function Addition of Figure (move from 2.
PAGE 1001
RL78/G1A APPENDIX A REVISION HISTORY (8/8) Edition Rev.0.03 Description Chapter Modification of description and addition of caution in 29.6.4 LVD circuit CHAPTER 29 characteristics ELECTRICAL Modification and addition of note 3 in 29.8 Flash Memory Programming Characteristics SPECIFICATIONS (TA = Modification of description in 29.
PAGE 1002
RL78/G1A User’s Manual: Hardware Publication Date: Rev.2.
PAGE 1003
http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
PAGE 1004
RL78/G1A R01UH0305EJ0200