Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1095 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.10.5 Digital Filter for Input on the RXDX12 Pin
Signals input through the RXDX12 pin can be passed through a digital filter before they are conveyed to the internal
circuits. The digital filter consists of three flip-flop circuit stages connected in series and a match-detecting circuit. The
CR2.DFCS[2:0] bits select the sampling clock for the RXDX12 pin input signals. If the outputs of all three latches
match, the given level is conveyed to subsequent circuits. If the levels do not match, the previous value is retained. In
other words, levels are confirmed as being the signal if they are retained for at least three cycles of the sampling clock but
judged to be noise rather than changes in the signal level if they change within three cycles of the sampling clock.
Figure
33.70
shows an example of operations with the digital filter.
Figure 33.70 Example of Operations with the Digital Filter
Sampling clock
RXDX12 input signal after
passing through the digital filter
Clock period selected by
DFCS[2:0]
Change in signal level is not recognized
due to not matching 3 times.
Delay in signal propagation:
up to 3 sampling-clock cycles
D
C
Q
Match-
detection
circuit
RXDX12 input
signal
PCLK/8
PCLK/16
PCLK/32
PCLK/64
PCLK/128
Sampling clock
Base clock
CR2.DFCS[2:0]
D
C
QD
C
Q
RXDX12 input signal