Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1076 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.54 Example of the Procedure for Master Transmission Operations in Simple I
2
C Mode
(with Transmission Interrupts and Reception Interrupts in Use)
End
Initialization
Start of transmission
[ 1 ]
No
Yes
STI interrupt?
[ 2 ]
Simultaneously set the SIMR3.IICSTAREQ
bit to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
00b
Write the slave address and value for the
R/W bit In the TDR register
No
Yes
No
Yes
SISR.IICACKR = 0?
[ 3 ]
Write transmit data In the TDR register
No
Yes
TXI interrupt?
No
Yes
All data transmitted?
No
Yes
STI interrupt?
Simultaneously set the SIMR3.IICSTPREQ
bit to 1 and the SIMR3.IICSCLS[1:0] and
IICSDAS[1:0] bits to 01b
Set the SIMR3.IICSTIF to 0, and set the
SIMR3.IICSCLS[1:0] and IICSDAS[1:0] bits to
11b
TXI interrupt?
[ 5 ]
[ 4 ]
If 10-bit slave addresses are in use, processing of [3] and [4]
is repeated twice.
[ 6 ]
[ 1 ] Initialization for simple I
2
C mode
For transmission, set the SCR.RIE bit to 0 (RXI and ERI
interrupts requests are disabled)
[ 2 ] Generate a start condition.
[ 3 ] Writing to the TDR register:
Writing the slave address and value for the R/W bit to the
TDR register.
[ 4 ] Confirming ACK response from the slave address:
Check the SISR.IICACKR bit. If its value is 0, it is indicated
that the slave device responded with ACK and operations
proceed. If its value is 1, it is indicated that there was no
response from a slave device so the next transition is to
generation of the stop condition.
[ 5 ] Steps for continuing with serial transmission:
When transmission is to continue, write further transmit data
to the TDR register.
Except for the first data to be transmitted, a TXI request can
activate the DMAC or DTC to handle writing of data to the
TDR register. In this case, ACK/NACK cannot be confirmed.
[ 6 ] Generation of a stop condition.
Note: In simple I
2
C mode, the TXI interrupt request is generated
when communication is completed, unlike the timing during
clock synchronous transmission.