Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1064 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.41 shows a sample flowchart of serial transmission.
Figure 33.41 Sample Smart Card Interface Transmission Flowchart
All the processing steps are automatically performed using a TXI interrupt request to activate the DTC or DMAC.
When the SSR.TEND flag is set to 1 in transmission, if the SCR.TIE bit is 1, a TXI interrupt request is generated. The
DTC or DMAC is activated by a TXI interrupt request if the TXI interrupt request is specified as a source of DTC or
DMAC activation beforehand, allowing transfer of transmit data. The TEND flag is automatically set to 0 when the DTC
or DMAC transfers the data.
If an error occurs, the SCI automatically retransmits the same data. During this retransmission, the TEND flag is kept to
0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or DMAC automatically transmit the specified
number of bytes, including retransmission in the case of error occurrence. However, since the ERS flag is not
automatically cleared, set the RIE bit to 1 beforehand to enable an ERI interrupt request to be generated at error
occurrence, and clear the ERS flag.
Initialization
No
Yes
Set the SCR.TIE, RIE, and TE
bits to 0
Start data transmission
Start
No
No
No
Yes
Yes
Yes
Yes
No
End
TXI interrupt
Error processing
Error processing
SSR.ERS flag = 0?
All transmit data written?
TXI interrupt
SSR.ERS flag = 0?
Write transmit data to the TDR
register