Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1055 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.31 shows a sample flowchart for serial data reception.
Figure 33.31 Example Flowchart of Serial Reception in Clock Synchronous Mode
Yes
End
No
Initialization
Start data reception
No
Yes
Set the SCR.RIE and RE bits to 0
Error processing
(Continued below)
Read receive data in the RDR register
No
Yes
SSR.ORER = 1
RXI interrupt
All data received?
Read the SSR.ORER flag
End
Error processing
Clear the SSR.ORER flag
Overrun error processing
[ 1 ]
[ 2 ]
[ 3 ]
[ 4 ]
[ 5 ]
[ 3 ]
[ 6 ]
Read the SSR.ORER flag
[ 7 ]
[ 8 ]
[ 1 ] SCI initialization:
Make input port-pin settings for pins to be used
as RXDn pins.
[ 2 ] [ 3 ] Receive error processing:
If a receive error occurs, read the SSR.ORER
flag, perform the relevant error processing, and
then set the ORER flag to 0. Data reception
cannot be resumed while the ORER flag is 1.
[ 4 ] Read the receive data in the RDR register once
in the receive data full interrupt (RXI) request
handling routine.
[ 5 ] Serial reception continuation procedure:
To continue serial reception, before the MSB (bit
7) of the current frame is received, finish reading
the receive data in the RDR register. The RDR
data can also be read by activating the DMAC or
DTC by an RXI interrupt request.
[ 6 ] Processing in response to an overrun error:
Read the RDR register. In combination with step
[ 7 ], this will make correct reception of the next
frame possible.
[ 7 ] Clearing the error flag:
Write 0 to the error flag.
[ 8 ] Confirming that the error flag is cleared:
Read the error flag to confirm that its value is 0.