Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1050 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.25 Example of Serial Data Transmission in Clock Synchronous Mode When the CTS Function is Not
Used at the Beginning of Transmission
Figure 33.26 Example of Serial Data Transmission in Clock Synchronous Mode When the CTS Function is
Used at the Beginning of Transmission
Synchronization clock
Serial data
TXI interrupt request
generated
TXI interrupt
request
generated
TXI interrupt flag
(IRn in ICU
*1
)
Data written to TDR in TXI
interrupt handling routine
SSR.TEND flag
SCR.TE bit
Data written to TDR in
TXI interrupt handling
routine
Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 7
1 frame
Bit 0
TXI interrupt
request generated
Data written to TDR in TXI
interrupt handling routine
TXI interrupt
request
generated
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.
Synchronization clock
1 frame
Serial data
TXI interrupt request
generated
TXI interrupt
Request generated
TXI interrupt flag
(IRn in ICU
*1
)
Data written to TDR in
TXI interrupt handling
routine
SSR.TEND flag
Bit 0 Bit 1 Bit 7 Bit 0
CTSn# pin
SCR.TE bit
Data written to TDR in
TXI interrupt handling
routine
TXI interrupt request
generated
Data written to TDR in TXI
interrupt handling routine
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.