Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1043 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.4.2 Multi-Processor Serial Data Reception
Figure 33.21 and Figure 33.22 are sample flowcharts of multi-processor data reception. When the SCR.MPIE bit is set
to 1, reading the communication data is skipped until reception of the communication data in which the multi-processor
bit is set to 1. When the communication data in which the multi-processor bit is set to 1 is received, the received data is
transferred to the RDR register (the RDRH and RDRL registers when 9-bit data length is selected). During this time, the
RXI interrupt request is generated. The other operations are the same as the operations in asynchronous mode.
Figure 33.20 is the example of operation for reception.
Figure 33.20 Example of SCI Reception (8-Bit Data/Multi-Processor Bit/1 Stop Bit)
MPIE
0
D0 D1 D7 1 1 0 D0 D1 D7 0 1
MPB
Data (Data1)
MPB
RXI interrupt request
(multi-processor
interrupt) generated
ID1
0 D0 D1 D7 1 1 0 D0 D1 D7 0 1
ID2 Data2ID1
Stop bit
Idle state
(mark state)
Data (ID1)
Start bitStop bitStart bit
RDR value
MPIE = 0
MPIE
RXI interrupt flag
(IRn In ICU
*1
)
RDR value
MPIE = 0
MPIE bit set to 1 again
when the received ID
does not match the ID of
the receiving station itself
RXI interrupt request not
generated. RDR retains
the state.
(a) When the received ID does not match the ID of the receiving station itself
(b) When the received ID matches the ID of the receiving station itself
RDR data read in RXI
interrupt handling
routine
MPB
Data (Data2)
MPB
Stop bit
Idle state
(mark state)
Data (ID2)
Start bitStop bitStart bit
RXI interrupt request
(multi-processor
interrupt) generated
Since the received ID matches
the ID of the receiving station
itself, reception continued and
data received in RXI interrupt
handling routine
MPIE bit set to 1 again
RDR data read in RXI
interrupt handling
routine
RXI interrupt flag
(IRn In ICU
*1
)
Note 1. Refer to section 15, Interrupt Controller (ICUb) for details on the corresponding interrupt vector number.