Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1021 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.28 Status Clear Register (STCR)
33.2.29 Control Field 0 Data Register (CF0DR)
The CF0DR register is an 8-bit readable and writable register that holds a value for comparison with Control Field 0.
Address(es): SCI12.STCR 0008 B328h
b7 b6 b5 b4 b3 b2 b1 b0
— — AEDCL BCDCL
PIBDC
L
CF1MC
L
CF0MC
L
BFDCL
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 BFDCL BFDF Clear Setting this bit to 1 clears the STR.BFDF flag. This bit is read as 0. R/W
b1 CF0MCL CF0MF Clear Setting this bit to 1 clears the STR.CF0MF flag. This bit is read as 0. R/W
b2 CF1MCL CF1MF Clear Setting this bit to 1 clears the STR.CF1MF flag. This bit is read as 0. R/W
b3 PIBDCL PIBDF Clear Setting this bit to 1 clears the STR.PIBDF flag. This bit is read as 0. R/W
b4 BCDCL BCDF Clear Setting this bit to 1 clears the STR.BCDF flag. This bit is read as 0. R/W
b5 AEDCL AEDF Clear Setting this bit to 1 clears the STR.AEDF flag. This bit is read as 0. R/W
b7, b6 — Reserved These bits are read as 0. The write value should be 0. R/W
Address(es): SCI12.CF0DR 0008 B329h
b7 b6 b5 b4 b3 b2 b1 b0
Value after reset:
00000000