Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1183 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.33 Examples of Master Arbitration-Lost Detection (MALE = 1)
Figure 35.34 Arbitration-Lost When a Start Condition is Generated (MALE = 1)
[When slave addresses conflict]
S
1 2345
Data
S 1 9
6
1
1
2 3 41 6
0
75
2 31
8
R
9 234567
Data
8
4 5
[When data transmission conflicts after general call address is sent]
S 1
1 2345
Data
2 3 4
SS 2 3 41 5
0
6 7 8 9
5
1
9
9
234567
000000
1
0
234567
000000
1
0
8
W
Address match
Address mismatch
8
W
Read ICDRR register
General call address match (0000 000b + W)
Transmit data mismatch
(Arbitration lost)
Release SCL/SDA
TRS
AL
MST
BBSY
GCA
RDRF
TRS
AL
MST
BBSY
AASy
TDRE
Transmit data mismatch
(Arbitration lost)
Release SCL/SDA
ACKACK
ACK
Clear AL flag to 0
Clear AL flag to 0
ACK ACK
Receive data
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
S
PCLK
S 1 S 8
R
9 12 12671
ACK
7-bit/10-bit slave address
ST = 1, BBSY = 1
Bus free (BBSY = 0) start condition generation (ST = 1) error Bus busy (BBSY =1) start condition generation (ST = 1) error
ST = 1,
BBSY = 1
TRS
AL
MST
BBSY
AASy
ST
Write 1 to ST bit Write 1 to ST bit Write 1 to ST bit
SDA mismatch
PCLK PCLK
TRS
AL
MST
BBSY
AASy
ST
TRS
AL
MST
BBSY
AASy
ST
ST = 1, BBSY = 1
SCL0
SDA0
SCL0
SDA0
SCL0
SDA0
SCL0
SCL0
SDA0 SDA0
SCL0
SDA0
SCL0