Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1179 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.8.2 NACK Reception Transfer Suspension Function
The RIIC has a function to suspend transfer operation when NACK is received in transmit mode (ICCR2.TRS bit is 1).
This function is enabled when the ICFER.NACKE bit is set to 1 (transfer suspension enabled). If the next transmit data
has already been written (ICSR2.TDRE flag is 0) when NACK is received, next data transmission at the falling edge of
the ninth SCL is automatically suspended. This prevents the SDA0 line output level from being held low when the MSB
of the next transmit data is 0.
If the data transmission is suspended (ICSR2.NACKF flag is 1) by this function, the following data transmission and data
reception are not started. To resume data transfer, set the NACKF flag to 0. In master transmit mode, restart data transfer
by setting the NACKF flag to 0 after generating a restart condition, or restart data transfer from a start condition after
generating a stop condition then setting the NACKF flag to 0.
Figure 35.31 Suspension of Data Transmission When NACK is Received (NACKE = 1)
[Master transmit mode]
SCL0
SDA0
BBSY
AASy
TRS
TDRE
NACKF
123456789 123456789
W# A7-bit slave address A#
Automatic low-hold (to prevent wrong transmission)
Write data to ICDRT register
(7-bit address + W#)
Write data to ICDRT
register (DATA 1)
Write 1 to SP bit
Clear NACKF flag
Transmission
suspended
Bus free time (ICBRL)
7-bit slave address
Write 1 to ST bit
Write data to ICDRT register
(7-bit address + W#)
W#
Write data to ICDRT
register (DATA 1)
S SP
[Slave transmit mode]
SCL0
SDA0
BBSY
AASy
TRS
TDRE
NACKF
123456789
Data (DATA 1) A#
Automatic low-hold
(to prevent wrong transmission)
Write data to ICDRT
register (DATA 1)
Write data to ICDRT
register (DATA 2)
Clear NACKF flag
Transmission
suspended
Bus free time (ICBRL)
S P
123456789
7-bit slave address R A
Address match
Transmit data (DATA 1)
Transmit data (7-bit address + W#)
Transmit data (7-bit address + W#)
Transmit data (DATA 1)
Transmit data (DATA 1)
Transmit data (DATA 2)