Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1177 of 1852
Nov 30, 2020
RX23W Group 35. I
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C-bus Interface (RIICa)
35.7.4 Host Address Detection
The RIIC has a function to detect the host address while the SMBus is operating. When the ICSER.HOAE bit is set to 1
while the ICMR3.SMBS bit is 1, the RIIC can detect the host address (0001 000b) in slave receive mode (bits MST and
TRS in the ICCR2 register are 00b).
When the RIIC detects the host address, the ICSR1.HOA flag is set to 1 at the rising edge of the ninth SCL, and at the
same time, the ICSR2.RDRF flag is set to 1 when the R/W# bit is 0 (Wr bit). This causes a receive data full interrupt
(RXI) to be generated. The HOA flag is used to recognize that the host address was sent from the smart battery or other
devices.
If the bit following the host address (0001 000b) is an Rd bit (R/W# bit is 1), the RIIC can also detect the host address.
After the host address is detected, the RIIC operates in the same manner as normal slave operation.
Figure 35.29 HOA Flag Set Timing during Reception of Host Address
Read ICDRR register
(Dummy read [7-bit address])
AAS2
AAS0
S
1
AAS1
9
ACK
BBSY
RDRF
234567
8 9
ACK
1
[Host address reception]
1
0
HOA
234567
001000
8
W
2345
Data (DATA 1) Data (DATA 2)
Read ICDRR register
(DATA 1)
Receive data (7-bit address) Receive data (DATA 1)
Host address match (0001 000b)
SCL0
SDA0