Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1175 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.7.3 Device-ID Address Detection
The RIIC module has a function to detect device-ID addresses complying with the I
2
C-bus specification. When the RIIC
receives 1111 100b as the first seven bits of the first byte following a start condition or a restart condition while the
ICSER.DIDE bit set to 1, the RIIC recognizes the address as a device-ID address, sets the ICSR1.DID flag to 1 on the
rising edge of the ninth SCL when the following R/W# bit is 0, and then compares the second and following bytes with
its own slave address. If the received address matches the value in the slave address register, the RIIC sets the
corresponding ICSR1.AASy flag (y = 0 to 2) to 1.
After that, when the first byte received after a start or restart condition is generated matches the device ID address (1111
100b) again and the following R/W# bit is 1, the RIIC does not compare the second and subsequent bytes and sets the
ICSR2.TDRE flag to 1.
In the device-ID address detection function, the RIIC sets the DID flag to 0 if a match with the RIIC’s own slave address
is not obtained or a match with the device ID address is not obtained after a match with the RIIC’s own slave address and
the detection of a restart condition. If the first byte after detection of a start or restart condition matches the device ID
address (1111 100b) and the R/W# bit is 0, the RIIC sets the DID flag to 1 and compares the second and subsequent bytes
with the RIIC’s slave address. If the R/W# bit is 1, the DID flag holds the previous value and the RIIC does not compare
the second and subsequent bytes. Therefore, the reception of a device-ID address can be checked by reading the DID flag
after confirming that TDRE flag is 1.
Furthermore, prepare the device-ID fields (3 bytes: 12 bits indicating the manufacturer + 9 bits identifying the part + 3
bits indicating the revision) that must be sent to the host after reception of a continuous device-ID field as normal data for
transmission. For details of the information that must be included in device-ID fields, contact NXP Semiconductors.