Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1172 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.7 Address Match Detection
The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7-
bit or 10-bit slave addresses.
35.7.1 Slave-Address Match Detection
The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address.
When the ICSER.SARyE bit (y = 0 to 2) is set to 1, the slave addresses set in registers SARUy and SARLy (y = 0 to 2)
can be detected.
When the RIIC detects a match with its set slave address, the corresponding ICSR1.AASy flag (y = 0 to 2) is set to 1 on
the rising edge of the ninth SCL, and the ICSR2.RDRF flag or the ICSR2.TDRE flag is set to 1 according to the level of
the R/W# bit. This causes a receive data full interrupt (RXI) or transmit data empty interrupt (TXI) to be generated. The
AASy flag is used to identify which slave address has been specified.
Figure 35.24 to Figure 35.26 show the AASy flag set timing in three cases.
Figure 35.24 AASy Flag Set Timing with 7-Bit Address Format Selected
TDRE
AASy
S
1 234567
7-bit slave address
8
W
1
8
R
9
ACK
TRS
9
ACK
BBSY
TDRE
AASy
TRS
BBSY
RDRF
RDRF
234567
Data (DATA 1)
8 9
ACK
S 1 234567
1 2345
234567 8 9
ACK
1
Read ICDRR register
(Dummy read [7-bit address])
Address match
[7-bit address format: Slave reception]
1 2345
[7-bit address format: Slave transmission]
7-bit slave address
Data (DATA 2)
Data (DATA 1) Data (DATA 2)
Receive data (7-bit address) Receive data (DATA 1)
Read ICDRR register
(DATA 1)
Write data to ICDRT
register (DATA 3)
Write data to ICDRT
register (DATA 1)
Write data to ICDRT
register (DATA 2)
Transmit data (DATA 2)Transmit data (DATA 1)
Address match
SCL0
SDA0
SCL0
SDA0