Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1162 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.12 Master Receive Operation Timing (1) (7-Bit Address Format, When RDRFS bit is 0)
Figure 35.13 Master Receive Operation Timing (2) (10-Bit Address Format, When RDRFS bit is 0)
Read ICDRR register
(Dummy read)
Read ICDRR register
(DATA 1)
Write data to ICDRT register
(7-bit address + R)
Write 1
to ST bit
X (ACK/NACK)
0 (ACK)
XXXX (Initial value/last data for reception) XXXX (Initial value/last data for reception)
7-bit address + R
Transmit data (7-bit address + R)
7-bit slave address
Automatic low hold
(to prevent wrong transmission)
TDRE
MST
TRS
BBSY
TEND
S 9
ST
START
ICDRT
ICDRS
DATA 1 DATA 2
1
b7
R
2
b6
3
b5
4
b4
5
b3
6
b2
7
b1
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
1
b7
2
b6
4
b4
3
b5
DATA 1 DATA 2
1
b7
RDRF
ICDRR DATA 1
98
b0
Master transmit mode Master receive mode
ACKBT
ACKBR
[3] [4] [5][2]
0 (ACK) 0 (ACK)
ACK
Receive data (7-bit address + R)
7-bit address + R
ACK
Receive data (DATA 1)
SCL0
SDA0
Write 1
to ST bit
Write data to ICDRT
register
(11110b + 2 bits + R)
0 (ACK)
XXXX (Initial value/last data for reception)
XXXX (Initial value/last data for reception)
Upper 10 bits + R
Upper 10 bits + R
Master transmit mode Master receive mode
Automatic low hold (to prevent wrong transmission)
Read ICDRR register
(Dummy read)
Upper 10 bits + W
TDRE
MST
TRS
BBSY
TEND
S
ST
START
ICDRT
ICDRS
DATA 1
W
7
b1
1
b7
2
b6
4
b4
3
b5
DATA 1
RDRF
ICDRR
Upper 10-bit addresses (11110b + 2 bits)
R
98
b0
2
b6
3
b5
4
b4
5
b3
1
b7
6
b2
Sr1
to
8 998
b0
1
to
7
b7 b1
Lower 10 bitsUpper 10 bits
RS
ACKBT
ACKBR
[3] [4][2]
Upper 10 bits + W
Lower 10 bits
0 (ACK) 0 (ACK)0 (ACK)
Write 1
to RS bit
Clear
START flag
Write data to
ICDRT register
(lower 8 bits)
Write data to ICDRT
register
(11110b + 2 bits + W)
Transmit data (lower 10 bits)Transmit data (upper 10 bits + W)
Transmit data (upper 10 bits + R)
Transmit data (upper 10 bits + R)
ACKACKACK
X (ACK/NACK)
Lower 10 bits
b7 b0
SCL0
SDA0