Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1157 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
Figure 35.7 Master Transmit Operation Timing (1) (7-Bit Address Format)
Figure 35.8 Master Transmit Operation Timing (2) (10-Bit Address Format)
Write data to
ICDRT register
(7-bit address + W)
Write data to
ICDRT register
(DATA 1)
Write data to
ICDRT register
(DATA 2)
7-bit address + W
Transmit data (DATA 2)Transmit data (7-bit address + W)
TDRE
MST
TRS
BBSY
TEND
S 9
Write data to
ICDRT register
(DATA 3)
8
b0
ST
START
ICDRT
ICDRS
7-bit address + W
DATA 1
DATA 1
DATA 2
DATA 3
DATA 2
Write 1
to ST bit
1
b7
7-bit slave address
W
2
b6
3
b5
4
b4
5
b3
6
b2
7
b1
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
1
b7
2
b6
4
b4
3
b5
DATA 1 DATA 2
1
b7
RDRF
ICDRR
9
ACKBT
ACKBR
0 (ACK)
X (ACK/NACK)
[3] [4]
[4]
[2] [4]
0 (ACK)
ACK
ACK
0 (ACK)
XXXX (Initial value/last data for reception)
Automatic low-hold (to prevent wrong transmission)
Transmit data (DATA 1)
SCL0
SDA0
Transmit data (upper 10 bits + W)
0 (ACK)
Write data to
ICDRT register
(11110b + 2
bits + W)
Write data to
ICDRT register
(lower 8 bits)
Write data to
ICDRT register
(DATA 1)
Write data to
ICDRT register
(DATA 2)
Write 1
to ST bit
RDRF
ICDRR
TDRE
MST
TRS
BBSY
TEND
S 9
ST
START
ICDRT
ICDRS
Upper 10 bits + W
Lower 10 bits
Lower 10 bits
DATA 1
DATA 2
DATA 1
Upper 10-bit addresses (11110b + 2 bits)
W
Lower 10-bit addresses
1
b7
2
b6
4
b4
5
b3
6
b2
7
b1
3
b5
8
b0
1
b7
2
b6
4
b4
3
b5
DATA 1
2
b6
3
b5
4
b4
5
b3
6
b2
8
b0
7
b1
1
b7
9
ACKBT
ACKBR
[3] [4] [4][2]
X (ACK/NACK)
Transmit data (lower 10 bits)
ACK
Transmit data (DATA 1)
ACK
Automatic low-hold (to prevent wrong transmission)
10-bit address + W
0 (ACK) 0 (ACK)
XXXX (Initial value/last data for reception)
SCL0
SDA0