Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1145 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
[Setting conditions]
When master arbitration-lost detection is enabled: ICFER.MALE = 1
• When the internal SDA output state does not match the SDA0 line level at the rising edge of SCL except for the
ACK period during data (including slave address) transmission in master transmit mode (when the SDA0 line is
driven low while the internal SDA output is high (the SDA0 pin is in the high-impedance state))
• When a start condition is detected while the ICCR2.ST bit is 1 (requests to generate a start condition) or the internal
SDA output state does not match the SDA0 line level
• When the ICCR2.ST bit is set to 1 (requests to generate a start condition) with the ICCR2.BBSY flag set to 1.
When NACK arbitration-lost detection is enabled: ICFER.NALE = 1
• When the internal SDA output state does not match the SDA0 line level at the rising edge of SCL in the ACK period
during NACK transmission in receive mode
When slave arbitration-lost detection is enabled: ICFER.SALE = 1
• When the internal SDA output state does not match the SDA0 line level at the rising edge of SCL except for the
ACK period during data transmission in slave transmit mode
[Clearing conditions]
• When 0 is written to the AL flag after reading AL = 1
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
×: Don’t care
START Flag (Start Condition Detection Flag)
[Setting condition]
• When a start condition (or a restart condition) is detected
[Clearing conditions]
• When 0 is written to the START bit after reading START = 1
• When a stop condition is detected
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
STOP Flag (Stop Condition Detection Flag)
[Setting condition]
• When a stop condition is detected
[Clearing conditions]
• When 0 is written to the STOP bit after reading STOP = 1
• When 1 is written to the ICCR1.IICRST bit to apply an RIIC reset or an internal reset
Table 35.4 Relationship between Arbitration-Lost Generation Sources and Arbitration-Lost Enable Functions
ICFER ICSR2
Error Arbitration-Lost Generation SourceMALE NALE SALE AL
1 × × 1 Start condition
generation error
When internal SDA output state does not match SDA0 line level when a
start condition is detected while the ICCR2.ST bit is 1
When ICCR2.ST bit is set to 1 with ICCR2.BBSY flag set to 1
1 Transmit data
mismatch
When transmit data (including slave address) does not match the bus
state in master transmit mode
×1×1NACK
transmission
mismatch
When ACK is detected during transmission of NACK in master receive
mode or slave receive mode
× × 1 1 Transmit data
mismatch
When transmit data does not match the bus state in slave transmit mode