Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1135 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.2.6 I
2
C-bus Function Enable Register (ICFER)
TMOE Bit (Timeout Function Enable)
This bit is used to enable or disable the timeout function.
For details on the timeout function, refer to
section 35.11.1, Timeout Function.
MALE Bit (Master Arbitration-Lost Detection Enable)
This bit is used to specify whether to use the arbitration-lost detection function in master mode. Normally, set this bit to
1.
NALE Bit (NACK Transmission Arbitration-Lost Detection Enable)
This bit is used to specify whether to cause arbitration to be lost when ACK is detected during transmission of NACK in
receive mode (such as when slaves with the same address exist on the bus or when two or more masters select the same
slave device simultaneously with different number of receive bytes).
SALE Bit (Slave Arbitration-Lost Detection Enable)
This bit is used to specify whether to cause arbitration to be lost when a value different from the value being transmitted
is detected on the bus in slave transmit mode (such as when slaves with the same address exist on the bus or when a
mismatch with the transmit data occurs due to noise).
Address(es): RIIC0.ICFER 0008 8305h
b7 b6 b5 b4 b3 b2 b1 b0
— SCLE NFE NACKE SALE NALE MALE TMOE
Value after reset:
01110010
Bit Symbol Bit Name Description R/W
b0 TMOE Timeout Function Enable 0: The timeout function is disabled.
1: The timeout function is enabled.
R/W
b1 MALE Master Arbitration-Lost
Detection Enable
0: Master arbitration-lost detection is disabled.
(Disables the arbitration-lost detection function and does not clear the
ICCR2.MST and TRS bits automatically when arbitration is lost.)
1: Master arbitration-lost detection is enabled.
(Enables the arbitration-lost detection function and clears the
ICCR2.MST and TRS bits automatically when arbitration is lost.)
R/W
b2 NALE NACK Transmission
Arbitration-Lost Detection
Enable
0: NACK transmission arbitration-lost detection is disabled.
1: NACK transmission arbitration-lost detection is enabled.
R/W
b3 SALE Slave Arbitration-Lost
Detection Enable
0: Slave arbitration-lost detection is disabled.
1: Slave arbitration-lost detection is enabled.
R/W
b4 NACKE NACK Reception Transfer
Suspension Enable
0: Transfer operation is not suspended during NACK reception (transfer
suspension disabled).
1: Transfer operation is suspended during NACK reception (transfer
suspension enabled).
R/W
b5 NFE Digital Noise Filter Enable 0: Digital noise filters are not used.
1: Digital noise filters are used.
R/W
b6 SCLE SCL Synchronization
Enable
0: SCL synchronization is disabled.
1: SCL synchronization is enabled.
R/W
b7 — Reserved This bit is read as 0. The write value should be 0. R/W