Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1131 of 1852
Nov 30, 2020
RX23W Group 35. I
2
C-bus Interface (RIICa)
35.2.4 I
2
C-bus Mode Register 2 (ICMR2)
Note 1. The DLCS bit setting of 1 (IICφ/2) only becomes valid when SCL pin is low. When SCL pin is high, the DLCS bit setting of 1
becomes invalid and the clock source becomes the internal reference clock (IICφ).
TMOS Bit (Timeout Detection Time Select)
This bit is used to select long mode or short mode for the timeout detection time when the timeout function is enabled
(ICFER.TMOE bit is 1). When this bit is set to 0, long mode is selected. When this bit is set to 1, short mode is selected.
In long mode, the timeout detection internal counter functions as a 16-bit counter. In short mode, the counter functions as
a 14-bit counter. While the SCL0 line is in the state that enables this counter as specified by bits TMOH and TMOL, the
counter counts up in synchronization with the internal reference clock (IICφ) as a count source.
For details on the timeout function, refer to
section 35.11.1, Timeout Function.
Address(es): RIIC0.ICMR2 0008 8303h
b7 b6 b5 b4 b3 b2 b1 b0
DLCS SDDL[2:0] — TMOH TMOL TMOS
Value after reset:
00000110
Bit Symbol Bit Name Description R/W
b0 TMOS Timeout Detection Time Select 0: Long mode is selected.
1: Short mode is selected.
R/W
b1 TMOL Timeout L Count Control 0: Count-up is disabled while the SCL0 line is low.
1: Count-up is enabled while the SCL0 line is low.
R/W
b2 TMOH Timeout H Count Control 0: Count-up is disabled while the SCL0 line is high.
1: Count-up is enabled while the SCL0 line is high.
R/W
b3 — Reserved This bit is read as 0. The write value should be 0. R/W
b6 to b4 SDDL[2:0] SDA Output Delay Counter
• When ICMR2.DLCS bit is 0 (IICφ)
b6 b4
0 0 0: No output delay
0 0 1: 1 IICφ cycle
0 1 0: 2 IICφ cycles
0 1 1: 3 IICφ cycles
1 0 0: 4 IICφ cycles
1 0 1: 5 IICφ cycles
1 1 0: 6 IICφ cycles
1 1 1: 7 IICφ cycles
• When ICMR2.DLCS bit is 1 (IICφ/2)
b6 b4
0 0 0: No output delay
0 0 1: 1 or 2 IICφ cycles
0 1 0: 3 or 4 IICφ cycles
0 1 1: 5 or 6 IICφ cycles
1 0 0: 7 or 8 IICφ cycles
1 0 1: 9 or 10 IICφ cycles
1 1 0: 11 or 12 IICφ cycles
1 1 1: 13 or 14 IICφ cycles
R/W
b7 DLCS SDA Output Delay Clock Source
Select
0: The internal reference clock (IICφ) is selected as the clock
source of the SDA output delay counter.
1: The internal reference clock divided by 2 (IICφ/2) is selected as
the clock source of the SDA output delay counter.*
1
R/W