Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1109 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
Figure 33.77 Example of Flowchart for Transition to Software Standby Mode during Transmission
Start data transmission
Initialization
SCR.TE = 1
SCR.TE bit = 0
Make transition to software standby mode
Cancel software standby mode
No
No
No
Yes
Yes
Yes
All data transmitted?
SSR.TEND = 1
Change operating mode?
Data transmission
[ 1 ]
[ 4 ]
Read TEND flag in SSR
Make the I/O port function settings
Make the I/O port function settings
[ 2 ]
[ 3 ]
[ 1 ] Data being transmitted is lost halfway. Data can be
normally transmitted from the CPU by setting the
SCR.TE bit to 1, reading the SSR register, and
writing data to the TDR register after canceling
software standby mode. However, if the DMAC or
DTC has been activated, the data remaining in the
DMAC or DTC will be transmitted when both the TE
and TIE bits in the SCR register are set to 1.
[ 2 ] Make the I/O port function settings to switch the
TXDn pin to operate as a general I/O port.
[ 3 ] Set the TIE and TEIE bits in the SCR register if they
are currently set to 1.
[ 4 ] This includes the setting for the module stop state.