Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1009 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.15 I
2
C Mode Register 1 (SIMR1)
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR register are 0 (both serial transmission and reception
are disabled).
SIMR1 is used to select simple I
2
C mode and the number of delay stages for the SSDA output.
IICM Bit (Simple I
2
C Mode Select)
In conjunction with the SCMR.SMIF bit, this bit selects the operating mode.
IICDL[4:0] Bits (SSDA Output Delay Select)
These bits are used to set a delay for output on the SSDAn pin relative to the falling edge of the output on the SSCLn pin.
The available delay settings range from no delay to 31 cycles, with the clock signal from the on-chip baud rate generator
as the base. The signal obtained by frequency-dividing PCLK by the divisor set in the SMR.CKS[1:0] bits is supplied as
the clock signal from the on-chip baud rate generator. Set these bits to 00000b unless operation is in simple I
2
C mode. In
simple I
2
C mode, set the bits to a value in the range from 00001b to 11111b.
Address(es): SCI1.SIMR1 0008 A029h, SCI5.SIMR1 0008 A0A9h, SCI8.SIMR1 0008 A109h, SCI12.SIMR1 0008 B309h
b7 b6 b5 b4 b3 b2 b1 b0
IICDL[4:0] — — IICM
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b0 IICM Simple I
2
C Mode Select
SMIF IICM
0 0: Asynchronous mode, Multi-processor mode,
Clock synchronous mode
(in asynchronous mode, synchronous, or simple SPI mode)
0 1: Simple I
2
C mode
1 0: Smart card interface mode
1 1: Setting prohibited.
R/W*
1
b2, b1 — Reserved These bits are read as 0. The write value should be 0. R/W
b7 to b3 IICDL[4:0] SSDA Output Delay Select (Cycles below are of the clock signal from the on-chip baud rate
generator.)
b7 b3
0 0 0 0 0: No output delay
00001: 0 to 1 cycle
0 0 0 1 0: 1 to 2 cycles
0 0 0 1 1: 2 to 3 cycles
0 0 1 0 0: 3 to 4 cycles
0 0 1 0 1: 4 to 5 cycles
::
1 1 1 1 0: 29 to 30 cycles
1 1 1 1 1: 30 to 31 cycles
R/W*
1