Users Manual
Table Of Contents
- 34. IrDA Interface
- 35. I2C-bus Interface (RIICa)
- 35.1 Overview
- 35.2 Register Descriptions
- 35.2.1 I2C-bus Control Register 1 (ICCR1)
- 35.2.2 I2C-bus Control Register 2 (ICCR2)
- 35.2.3 I2C-bus Mode Register 1 (ICMR1)
- 35.2.4 I2C-bus Mode Register 2 (ICMR2)
- 35.2.5 I2C-bus Mode Register 3 (ICMR3)
- 35.2.6 I2C-bus Function Enable Register (ICFER)
- 35.2.7 I2C-bus Status Enable Register (ICSER)
- 35.2.8 I2C-bus Interrupt Enable Register (ICIER)
- 35.2.9 I2C-bus Status Register 1 (ICSR1)
- 35.2.10 I2C-bus Status Register 2 (ICSR2)
- 35.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2)
- 35.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2)
- 35.2.13 I2C-bus Bit Rate Low-Level Register (ICBRL)
- 35.2.14 I2C-bus Bit Rate High-Level Register (ICBRH)
- 35.2.15 I2C-bus Transmit Data Register (ICDRT)
- 35.2.16 I2C-bus Receive Data Register (ICDRR)
- 35.2.17 I2C-bus Shift Register (ICDRS)
- 35.3 Operation
- 35.4 SCL Synchronization Circuit
- 35.5 SDA Output Delay Function
- 35.6 Digital Noise Filters
- 35.7 Address Match Detection
- 35.8 Automatic Low-Hold Function for SCL
- 35.9 Arbitration-Lost Detection Functions
- 35.10 Start Condition/Restart Condition/Stop Condition Generating Function
- 35.11 Bus Hanging
- 35.12 SMBus Operation
- 35.13 Interrupt Sources
- 35.14 Initialization of Registers and Functions When a Reset is Applied or a Condition is Detected
- 35.15 Event Link Function (Output)
- 35.16 Usage Notes
- 36. CAN Module (RSCAN)
R01UH0823EJ0110 Rev.1.10 Page 1008 of 1852
Nov 30, 2020
RX23W Group 33. Serial Communications Interface (SCIg, SCIh)
33.2.14 Noise Filter Setting Register (SNFR)
Note 1. Writing to these bits is only possible when the RE and TE bits in the SCR register are 0 (serial reception and transmission
disabled).
NFCS[2:0] Bits (Noise Filter Clock Select)
These bits select the sampling clock for the digital noise filter. To use the noise filter in asynchronous mode, set these bits
to 000b. In simple I
2
C mode, set the bits to a value in the range from 001b to 100b.
Address(es): SCI1.SNFR 0008 A028h, SCI5.SNFR 0008 A0A8h, SCI8.SNFR 0008 A108h, SCI12.SNFR 0008 B308h
b7 b6 b5 b4 b3 b2 b1 b0
————— NFCS[2:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b2 to b0 NFCS[2:0] Noise Filter Clock Select In asynchronous mode, the standard setting for the base clock is as
follows.
b2 b0
0 0 0: The clock signal divided by 1 is used with the noise filter.
In simple I
2
C mode, the standard settings for the clock source of the
on-chip baud rate generator selected by the SMR.CKS[1:0] bits are
given below.
b2 b0
0 0 1: The clock signal divided by 1 is used with the noise filter.
0 1 0: The clock signal divided by 2 is used with the noise filter.
0 1 1: The clock signal divided by 4 is used with the noise filter.
1 0 0: The clock signal divided by 8 is used with the noise filter.
Settings other than above are prohibited.
R/W*
1
b7 to b3 — Reserved These bits are read as 0. The write value should be 0. R/W