User's Manual

R01UH0823EJ0110 Rev.1.10 Page 379 of 1852
Nov 30, 2020
RX23W Group 18. DMA Controller (DMACA)
18.3.8 Starting DMA Transfer
Setting the DTE bit in DMCNT of DMACm to 1 (DMA transfer enabled) and setting the DMST bit in DMAST to 1
(DMAC start enabled) enable DMA transfer of channel m (m = 0 to 3).
Another activation request cannot be accepted during the transfer of other DMAC channel or DTC. When the proceeding
transfer is completed, channel arbitration is performed where a DMA transfer request of the highest priority channel is
accepted and DMA transfer of the channel starts. When DMA transfer starts, the ACT bit in DMSTS of DMACm is set
to 1 (the DMAC is in the active state).
18.3.9 Registers during DMA Transfer
The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and
the transfer state. The registers to be updated are DMSAR, DMDAR, DMCRA, DMCRB, DMCNT, and DMSTS of
DMACm.
(1) DMA Source Address Register (DMACm.DMSAR)
When data has been transferred in response to one transfer request, the contents of DMSAR are updated to the address to
be accessed by the next transfer request.
For details on register update operation in each transfer mode, refer to Table 18.3 to Table 18.5.
(2) DMA Destination Address Register (DMACm.DMDAR)
When data has been transferred in response to one transfer request, the contents of DMDAR are updated to the address to
be accessed by the next transfer request.
For details on register update operation in each transfer mode, refer to Table 18.3 to Table 18.5.
(3) DMA Transfer Count Register (DMACm.DMCRA)
When data has been transferred in response to one transfer request, the count value is updated. The update operation
depends on the transfer mode selected.
For details on register update operation in each transfer mode, refer to Table 18.3 to Table 18.5.
(4) DMA Block Transfer Count Register (DMACm.DMCRB)
When data has been transferred in response to one transfer request, the count value is updated. The update operation
depends on the transfer mode selected.
For details on register update operation in each transfer mode, refer to Table 18.3 to Table 18.5.
(5) DMA Transfer Enable Bit (DMACm.DMCNT.DTE)
Although the DMACm.DMCNT.DTE bit enables or disables data transfer by the register write access, it is automatically
cleared to 0 by the DMAC according to the DMA transfer state.
The conditions for clearing this bit by the DMAC are as follows:
• When the specified total volume of data transfer is completed
• When DMA transfer is stopped by the repeat size end interrupt
• When DMA transfer is stopped by the extended repeat area overflow interrupt
Writing to the registers for the channels when the corresponding DMACm.DMCNT.DTE bit is set to 1 is prohibited
(except for DMACm.DMCNT). In this case, writing must be performed after the bit is cleared to 0.