User's Manual

R01UH0823EJ0110 Rev.1.10 Page 316 of 1852
Nov 30, 2020
RX23W Group 16. Buses
Note: The above applies when the priority order of the buses is fixed.
The priority order of internal main bus 1 and another bus (internal main bus 2) can be toggled by the bus priority control register
(BUSPRI) (round-robin method).
16.2.4 Internal Peripheral Buses
Connection of peripheral modules to the internal peripheral buses is as described in Table 16.4.
Requests for bus mastership from the CPU (internal main bus 1) and other bus masters (internal main bus 2) are
arbitrated through internal peripheral buses 1 to 4, and 6.
The priority order of two internal main buses can be set using the bus priority control register (BUSPRI). The priority
order can be set with the internal peripheral bus 1 priority control bits (BUSPRI.BPIB[1:0]), internal peripheral bus 2 and
3 priority control bits (BUSPRI.BPGB[1:0]), internal peripheral bus 4 priority control bits (BUSPRI.BPHB[1:0]), and
internal peripheral bus 6 priority control bits (BUSPRI.BPFB[1:0]) for the corresponding internal peripheral buses.
When the priority order is fixed, internal main bus 2 has priority over internal main bus 1. When the priority order is
toggled, a bus has a lower priority when the request of that bus is accepted (round-robin method).
The order of accepting requests may change depending on the BUSPRI setting (Refer to Figure 16.2).
Table 16.3 Order of Priority for Bus Masters
Priority Internal main buses Bus Master
High
Low
2DMAC
DTC
1CPU
Table 16.4 Connection of Peripheral Modules to the Internal Peripheral Buses
Type of Bus Peripheral Modules
Internal peripheral bus 1 DTC, DMAC, interrupt controller, and bus error monitoring section
Internal peripheral bus 2 Peripheral modules other than those connected to internal peripheral buses 1, 3, and 4
Internal peripheral bus 3 USB0, RSCAN, and CTSU
Internal peripheral bus 4 MTU2
Internal peripheral bus 6 Flash control module and E2 DataFlash