User's Manual

R01UH0823EJ0110 Rev.1.10 Page 245 of 1852
Nov 30, 2020
RX23W Group 11. Low Power Consumption
11.2.8 Sleep Mode Return Clock Source Switching Register (RSTCKCR)
Note: Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.
Note 1. HOCO can only be selected when entering high-speed operating mode.
RSTCKCR is used to control clock source switching at exit from sleep mode.
When exit from sleep mode is initiated by setting RSTCKCR, the main clock oscillator stop bit in the main clock
oscillator control register (MOSCCR.MOSTP), the HOCO stop bit in the high-speed on-chip oscillator control register
(HOCOCR.HCSTP), and the LOCO stop bit in the low-speed on-chip oscillator control register (LOCOCR.LCSTP) are
automatically modified to the operating state corresponding to the clock source to be used after transition. The value of
the RSTCKSEL[2:0] bits is automatically reloaded to the clock source select bits in system clock control register 3
(SCKCR3.CKSEL[2:0]).
RSTCKSEL[2:0] Bits (Sleep Mode Return Clock Source Select)
The RSTCKSEL[2:0] bits select the clock source to be used at exit from sleep mode.
The clock source selected by the RSTCKSEL[2:0] bits is enabled only when the RSTCKEN bit is 1.
As shown in Figure 11.2, Operating Modes, when returning from sleep mode to high-speed operating mode, the
LOCO, HOCO, or main clock oscillator can be selected. When returning from sleep mode to middle-speed operating
mode, the LOCO or main clock oscillator can be selected. However, in this case, the frequency of each clock (ICLK,
FCLK, PCLKA, PCLKB, and PCLKD) must be lower than 12 MHz when the power supply voltage is 2.4 V or above,
and lower than 8 MHz when the voltage is below 2.4 V.
Note 1. The frequency of each clock (ICLK, FCLK, PCLKA, PCLKB, and PCLKD) must be lower than 12 MHz when the power supply
voltage is 2.4 V or above, and lower than 8 MHz when the voltage is below 2.4 V.
Address(es): 0008 00A1h
b7 b6 b5 b4 b3 b2 b1 b0
RSTCK
EN
———— RSTCKSEL[2:0]
Value after reset:
00000000
Bit Symbol Bit Name Description R/W
b2 to b0 RSTCKSEL
[2:0]
Sleep Mode Return Clock
Source Select
b2 b0
0 0 0: LOCO is selected
0 0 1: HOCO is selected*
1
0 1 0: Main clock oscillator is selected
Settings other than above are prohibited when the RSTCKEN bit is 1.
R/W
b6 to b3 — Reserved These bits are read as 0. The write value should be 0. R/W
b7 RSTCKEN Sleep Mode Return Clock
Source Switching Enable
0: Clock source switching at exit from sleep mode is disabled
1: Clock source switching at exit from sleep mode is enabled
R/W
Table 11.5 When Exiting Sleep Mode to High-Speed Operating Mode and Middle-Speed Operating Mode
Operating Mode during Sleep
Clock Source
during Sleep RSTCKSEL
Operating Mode
after Exiting
Clock Source after
Exiting
High-speed operating mode or
low-speed operating mode
after exit from high-speed
operating mode
Sub-clock oscillator 000b (LOCO) High-speed
operating mode
LOCO
001b (HOCO) HOCO
010b (main clock oscillator) Main clock oscillator
Middle-speed operating mode
or low-speed operating mode
after exit from middle-speed
operating mode
Sub-clock oscillator 000b (LOCO) Middle-speed
operating mode
LOCO
010b (main clock oscillator) Main clock oscillator*
1