User's Manual

R01UH0823EJ0110 Rev.1.10 Page 208 of 1852
Nov 30, 2020
RX23W Group 9. Clock Generation Circuit
9.6 Oscillation Stop Detection Function
9.6.1 Oscillation Stop Detection and Operation after Detection
The oscillation stop detection function is used to detect the main clock oscillator stop and to supply LOCO clock pulses
from the low-speed on-chip oscillator as the system clock source instead of the main clock.
An oscillation stop detection interrupt request can be generated when an oscillation stop is detected. In addition, the
MTU output can be forcedly driven to the high-impedance on the detection. For details, refer to section 23, Multi-
Function Timer Pulse Unit 2 (MTU2a) and section 24, Port Output Enable 2 (POE2a).
In the MCU, the main clock oscillation stop is detected when the input clock remains to be 0 or 1 for a certain period, for
example, due to a malfunction of the main clock oscillator (refer to section 51, Electrical Characteristics).
When an oscillation stop is detected, the main clock selected by the clock source select bits (SCKCR3.CKSEL[2:0]) is
switched to the LOCO clock by the corresponding selectors in the former stage. Therefore, if an oscillation stop is
detected with the main clock selected as the system clock source, the system clock source is switched to the LOCO clock
without a change of CKSEL[2:0].
If an oscillation stop is detected while the PLL clock is selected by the clock source select bits (SCKCR3.CKSEL[2:0])
in system clock control register 3, the SCKCR3.CKSEL[2:0] bit value does not change and the PLL clock remains the
system clock source. However, the frequency becomes a free-running oscillation frequency.
Also, if an oscillation stop is detected while the USB-dedicated PLL clock is selected by the UPLLCR.UCKPLLSEL bit,
the set value of these bits does not change and the USB-dedicated PLL clock remains the UCLK clock source. However,
the frequency becomes a free-running oscillation frequency.
Switching between the main clock and LOCO clock is controlled by the oscillation stop detection flag
(OSTDSR.OSTDF). The clock source is switched to the LOCO clock when the OSTDF flag is 1, and is switched to the
main clock again when the OSTDF flag is set to 0. At this time, if the main clock or PLL clock is selected with the
CKSEL[2:0] bits, the OSTDF flag cannot be set to 0. To switch the clock source to the main clock or PLL clock again
after the oscillation stop detection, set the CKSEL[2:0] bits to a clock source other than the main clock or PLL clock and
set the OSTDF flag to 0. After that, check that the OSTDF flag is not 1, and then set the CKSEL[2:0] bits to the main
clock or PLL clock after the specified oscillation stabilization time has elapsed.
After a reset is released, the main clock oscillator is stopped and the oscillation stop detection function is disabled. To
enable the oscillation stop detection function, activate the main clock oscillator and write 1 to the oscillation stop
detection function enable bit (OSTDCR.OSTDE) after a specified oscillation stabilization time has elapsed.
The oscillation stop detection function is provided against the main clock stop by an external cause. Therefore, the
oscillation stop detection function should be disabled before the main clock oscillator is stopped by the software or a
transition is made to software standby mode.
When the system clock with the main clock selected as the system clock source, CAC main clock (CACMCLK), SSI
clock (SSISCK), and CAN clock (CANMCLK) are selected, these clocks are switched to the LOCO clock by the
oscillation stop detection. The system clock (ICLK) frequency during the LOCO clock operation is specified by the
LOCO oscillation frequency and the division ratio set by the system clock (ICLK) select bits (SCKCR.ICK[3:0]).
When the PLL clock is selected as the system clock source and the USB-dedicated PLL clock is selected as the UCLK
source, these clocks operate at the PLL free-running frequency by the oscillation stop detection.