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R01UH0823EJ0110 Rev.1.10 Page 488 of 1852
Nov 30, 2020
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
BFA Bit (Buffer Operation A)
This bit specifies normal operation for the TGRA register or buffered operation of the combination of registers TGRA
and TGRC. When the TGRC register is used as a buffer register, the TGRC input capture/output compare does not take
place in modes other than complementary PWM mode, but compare match with the TGRC register occurs in
complementary PWM mode. If a compare match occurs on MTU4 in the Tb interval in complementary PWM mode, the
MTU4.TIER.TGIEC bit should be set to 0.
When MTU3 or MTU4 is set to reset-synchronized PWM mode or complementary PWM mode, the buffer operation
conforms to the MTU3 setting. Set the MTU4.TMDR.BFA bit to 0.
In MTU1 and MTU2, which have no TGRC register, this bit is reserved. It is read as 0. The write value should be 0.
Refer to
Figure 23.40 for an illustration of the Tb interval in complementary PWM mode.
BFB Bit (Buffer Operation B)
This bit specifies normal operation for the TGRB register or buffered operation of the combination of registers TGRB
and TGRD. When the TGRD register is used as a buffer register, the TGRD input capture/output compare does not take
place in modes other than complementary PWM mode, but compare match with the TGRD register occurs in
complementary PWM mode. If a compare match occurs in the Tb interval in complementary PWM mode, the
MTU3.TIER.TGIED or MTU4.TIER.TGIED bit should be set to 0.
When MTU3 or MTU4 is set to reset-synchronized PWM mode or complementary PWM mode, the buffer operation
conforms to the MTU3 setting. Set the MTU4.TMDR.BFB bit to 0.
In MTU1 and MTU2, which have no TGRD register, this bit is reserved. It is read as 0. The write value should be 0.
Refer to
Figure 23.40 for an illustration of the Tb interval in complementary PWM mode.
BFE Bit (Buffer Operation E)
This bit specifies normal operation or buffered operation for registers MTU0.TGRE and MTU0.TGRF. Compare match
with the TGRF register occurs even when the TGRF register is used as a buffer register.
In MTU1 to MTU4, this bit is reserved. It is read as 0. The write value should be 0.