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R01UH0823EJ0110 Rev.1.10 Page 597 of 1852
Nov 30, 2020
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
(2) Output Compare Output Timing
A compare match signal is generated in the final state in which the TCNT counter and the TGR register match (the point
at which the count value matched is updated by the TCNT counter). When a compare match signal is generated, the value
set in the TIOR register is output to the output compare output pin (MTIOC pin). After a match between the TCNT
counter and the TGR register, the compare match signal is not generated until the TCNT count clock is generated.
Figure 23.81 shows the output compare output timing (normal mode or PWM mode) and Figure 23.82 shows the
output compare output timing (complementary PWM mode or reset-synchronized PWM mode).
Figure 23.81 Output Compare Output Timing (Normal Mode or PWM Mode)
Figure 23.82 Output Compare Output Timing (Complementary PWM Mode or Reset-Synchronized PWM Mode)
N
N + 1
N
TGR
TCNT
TCNT count clock
Compare match signal
MTIOC pin
PCLK
TCNT count clock
TCNT
TGR
Compare match signal
MTIOC pin
PCLK
N
N + 1
N