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R01UH0823EJ0110 Rev.1.10 Page 565 of 1852
Nov 30, 2020
RX23W Group 23. Multi-Function Timer Pulse Unit 2 (MTU2a)
(g) PWM Cycle Setting
In complementary PWM mode, the PWM cycle is set in two registers — the MTU3.TGRA register, in which the
MTU3.TCNT counter upper limit value is set, and the TCDR register, in which the MTU4.TCNT counter upper limit
value is set. The settings should be made so as to achieve the following relationship between these two registers:
With dead time: MTU3.TGRA setting = TCDR setting + TDDR setting
Without dead time: MTU3.TGRA setting = TCDR setting + 1
The settings should be made so as to achieve the following relationship between registers TCDR and TDDR.
TCDR setting > TDDR setting × 2 + 2
The MTU3.TGRA and TCDR settings are made by setting values in buffer registers MTU3.TGRC and TCBR. When
data is written to the MTU4.TGRD register to enable transfers, the values set in registers MTU3.TGRC and TCBR are
transferred simultaneously to registers MTU3.TGRA and TCDR with the transfer timing selected with the
TMDR.MD[3:0] bits.
The new PWM cycle is reflected from the next cycle when data is updated at the crest, or from the current cycle when
updated in the trough.
Figure 23.42 illustrates the operation when the PWM cycle is updated at the crest.
Refer to the following section
(h) Register Data Updating, for the method of updating the data in each buffer register.
Figure 23.42 Example of PWM Cycle Updating
(h) Register Data Updating
In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be
written to the buffer register at any time. There are five registers (PWM duty and PWM cycle registers) that have buffer
registers and can be updated during operation.
There is a temporary register between each of these registers and its buffer register. While subcounter TCNTS is not
counting, if buffer register data is updated, the temporary register value also changes. Data is not transferred from buffer
registers to temporary registers while the TCNTS counter is counting; in this case, the value written to a buffer register is
transferred after the TCNTS counter halts.
The temporary register value is transferred to the compare register at the data update timing set with the TMDR.MD[3:0]
bits.
Figure 23.43 shows an example of data updating in complementary PWM mode. This example shows the mode in
which data is updated at both the counter crest and trough.
When updating buffer register data, be sure to write to the MTU4.TGRD register at the end of the update. Data is
transferred from buffer registers to the temporary registers simultaneously for all five registers after the write to the
MTU4.TGRD register.
Even when not updating all five registers or when not updating the MTU4.TGRD data, be sure to write to the
Counter value
MTU3.TGRC
update
MTU3.TGRA
update
MTU3.TGRA
Time
MTU3.TCNT
MTU4.TCNT