How-To Guide

R01UH0823EJ0110 Rev.1.10 Page 874 of 1852
Nov 30, 2020
RX23W Group 32. USB 2.0 Host/Function Module (USBc)
CURPIPE[3:0] Bits (FIFO Port Access Pipe Select)
The CURPIPE[3:0] bits specify the pipe number using which data is read or written through the D0FIFO port or D1FIFO
port.
After writing to these bits, read these bits to check that the written value agrees with the read value before proceeding to
the next process.
Do not set the same pipe number to the CURPIPE[3:0] bits in the CFIFOSEL, D0FIFOSEL, and D1FIFOSEL registers.
Even if an attempt is made to modify the setting of these bits during access to the FIFO buffer, the current access setting
is retained until the access is completed. Then, the modification becomes effective, thus enabling continuous access.
MBW Bit (FIFO Port Access Bit Width)
The MBW bit specifies the bit width for accessing the D0FIFO port or D1FIFO port.
When the selected pipe is in the receiving direction, once reading data is started after setting this bit, this bit should not
be modified until all the data has been read.
When the selected pipe is in the receiving direction, set the CURPIPE[3:0] bits to a different value once, and then set
these bits and the MBW bit simultaneously. For the procedure for modifying the CURPIPE[3:0] bits, follow the
description of these bits.
When the selected pipe is in the transmitting direction, the bit width cannot be changed from 8-bit width to 16-bit width
while data is being written to the buffer memory.
An odd number of bytes can also be written through byte-access control even when 16-bit width is selected.
DREQE Bit (DMA/DTC Transfer Request Enable)
The DREQE bit enables or disables the DMA/DTC transfer request to be issued.
Before setting the DREQE bit to 1 to enable the DMA/DTC transfer request to be issued, set the CURPIPE[3:0] bits.
When modifying the setting of the CURPIPE[3:0] bits, set this bit to 0 first.
DCLRM Bit (Automatic FIFO Buffer Memory Clear Mode after Selected Pipe is Read)
The DCLRM bit enables or disables the buffer memory to be cleared automatically after data in the selected pipe has
been read.
With this bit set to 1, the USB sets the BCLR bit to 1 for the FIFO buffer of the selected pipe on receiving a zero-length
packet while the FIFO buffer assigned to the selected pipe is empty, or on receiving a short packet and reading the data
while the PIPECFG.BFRE bit is 1.
When using the USB with the SOFCFG.BRDYM bit set to 1, set this bit to 0.
REW Bit (Buffer Pointer Rewind)
The REW bit specifies whether or not to rewind the buffer pointer.
When the selected pipe is in the receiving direction, setting the REW bit to 1 while the FIFO buffer is being read allows
re-reading the FIFO buffer from the first data (in double buffer mode, re-reading the currently-read FIFO buffer plane
from the first data is allowed).
Do not set the REW bit to 1 simultaneously with modifying the CURPIPE[3:0] bits. Before setting the REW bit to 1, be
sure to check that the FRDY flag is 1.
To re-write to the FIFO buffer again from the first data for the pipe in the transmitting direction, use the BCLR bit.
RCNT Bit (Read Count Mode)
The RCNT bit specifies the read mode for the value in the CFIFOCTR.DTLN bit.
When accessing DnFIFO with the PIPECFG.BFRE bit set to 1, set the RCNT bit to 0.