How-To Guide

Table Of Contents
R01UH0823EJ0110 Rev.1.10 Page 857 of 1852
Nov 30, 2020
RX23W Group 31. Independent Watchdog Timer (IWDTa)
Figure 31.6 shows the IWDT refresh-operation waveforms when PCLK > IWDTCLK and clock divide ratio =
IWDTCLK.
Figure 31.6 IWDT Refresh Operation Waveforms (IWDTCR.CKS[3:0] = 0000b, IWDTCR.TOPS[1:0] = 11b)
Invalid
Valid
Refreshing
Peripheral module
clock (PCLK)
IWDT-dedicated
clock (IWDTCLK)
Data written to
IWDTRR register
IWDTRR register write
signal (internal signal)
IWDTRR register
Refresh
synchronization signal
Refresh signal
(after synchronization
with IWDTCLK)
Counter value
n+2 n+1 n n-1 n-2 n-3
FFhFFh 00h 00h
Refresh request
00h 54h 00h FFh
FFh
07FFh