Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1234 of 1852
Nov 30, 2020
RX23W Group 36. CAN Module (RSCAN)
RFIF Flag (Receive FIFO Interrupt Request Flag)
This flag becomes 1 when the receive FIFO interrupt request generation conditions set by the RFCCm.RFIGCV[2:0] bits
(m = 0, 1) and the RFCCm.RFIM bit are met. This flag becomes 0 in global reset mode or by writing 0 to this flag.
Modify this bit only in global operating mode or global test mode.
RFMC[5:0] Flags (Receive FIFO Unread Message Counter)
These flags indicate the number of unread messages in the receive FIFO buffer. This flag becomes 00h when the
RFCCm.RFE bit is set to 0.
36.2.36 Receive FIFO Pointer Control Register m (RFPCTRm) (m = 0, 1)
RFPC[7:0] Bits (Receive FIFO Pointer)
When the RFPC[7:0] bits are set to FFh, the read pointer moves to the next unread message in the receive FIFO buffer.
At this time, the RFSTSm.RFMC[5:0] (receive FIFO unread message counter) value is decremented. Read the RFIDLm,
RFIDHm, RFTSm, RFPTRm, and RFDF0m to RFDF3m registers to read messages in the receive FIFO buffer, and then
write FFh to the RFPC[7:0] bits.
Write FFh to these bits when the RFCCm.RFE bit is set to 1 (receive FIFO buffers are used) and the RFSTSm.RFEMP
flag is 0 (the receive FIFO buffer contains unread messages).
Address(es): RSCAN.RFPCTR0 000A 8348h, RSCAN.RFPCTR1 000A 834Ah
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
———————— RFPC[7:0]
Value after reset:
0000000000000000
Bit Symbol Bit Name Description R/W
b7 to b0 RFPC[7:0] Receive FIFO Pointer When these bits are set to FFh, the read pointer moves to the
next unread message in the receive FIFO buffer. The setting
for these bits must be FFh.
W
b15 to b8 — Reserved The write value should be 0. W