Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1406 of 1852
Nov 30, 2020
RX23W Group 38. Serial Peripheral Interface (RSPIa)
(4) Burst Transfer
If the SPCMD0.CPHA bit is 1, continuous serial transfer (burst transfer) can be executed while retaining the assertion
state for the SSLA0 input signal. If the CPHA bit is 1, the period from the first RSPCKA edge to the sampling timing for
the reception of the final bit in an SSLA0 signal active state corresponds to a serial transfer period. Even when the
SSLA0 input signal remains at the active level, the RSPI can accommodate burst transfers because it can detect the start
of an access.
If the CPHA bit is 0, the second and subsequent serial transfers during burst transfer cannot be executed correctly.
(5) Initialization Flowchart
Figure 38.39 is a flowchart illustrating an example of initialization in SPI operation when the RSPI is used in slave
mode. For a description of how to set up the interrupt controller, DMAC, and I/O ports, refer to the descriptions given in
the individual blocks.
Figure 38.39 Example of Initialization Flowchart in Slave Mode (SPI Operation)
• Sets number of frames to be used.
Set RSPI slave select polarity
register (SSLP)
Set RSPI data control
register (SPDCR)
Set DMAC
Set I/O ports
Set RSPI control register
(SPCR)
Set RSPI command register 0
(SPCMD0)
Set interrupt controller
• Sets polarity of SSL0 input signal
(when using an interrupt)
(when using the DMAC)
• Sets MSB or LSB first.
• Sets data length.
• Sets clock phase.
• Sets clock polarity.
• Sets slave mode.
• Sets mode fault error detection.
• Sets interrupt mask.
• Sets RSPI mode.
• Sets parity function.
• Sets interrupt mask.
Set RSPI control register 2 (SPCR2)
Read RSPI control register (SPCR)
Start of initialization in
slave mode
End of initialization in
slave mode
Sets polarity of SSLAi input signal