Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1405 of 1852
Nov 30, 2020
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.3.10.2 Slave Mode Operation
(1) Starting a Serial Transfer
If the SPCMD0.CPHA bit is 0, when detecting an SSLA0 input signal assertion, the RSPI needs to start driving valid
data to the MISOA output signal. For this reason, when the CPHA bit is 0, the assertion of the SSLA0 input signal
triggers the start of a serial transfer.
If the CPHA bit is 1, when detecting the first RSPCKA edge in an SSLA0 signal asserted condition, the RSPI needs to
start driving valid data to the MISOA output signal. For this reason, when the CPHA bit is 1, the first RSPCKA edge in
an SSLA0 signal asserted condition triggers the start of a serial transfer.
When detecting the start of a serial transfer in a condition in which the shift register is empty, the RSPI changes the status
of the shift register to “full”, so that data cannot be copied from the transmit buffer to the shift register when serial
transfer is in progress. If the shift register was full before the serial transfer started, the RSPI leaves the status of the shift
register unchanged, in the full state.
Irrespective of the CPHA bit setting, the timing at which the RSPI starts driving of the MISOA output signal is the
SSLA0 signal assertion timing. The data which is output by the RSPI is either valid or invalid, depending on the CPHA
bit setting.
For details on the RSPI transfer format, refer to
section 38.3.5, Transfer Format. The polarity of the SSLA0 input
signal depends on the setting of the SSLP.SSL0P bit.
(2) Terminating a Serial Transfer
Irrespective of the SPCMD0.CPHA bit, the RSPI terminates the serial transfer after detecting an RSPCKA edge
corresponding to the final sampling timing. When free space is available in the receive buffer (the SPRF flag is 0), upon
termination of serial transfer the RSPI copies received data from the shift register to the receive buffer of the SPDR
register. Upon termination of a serial transfer the RSPI changes the status of the shift register to “empty”, regardless of
the receive buffer state. A mode fault error occurs if the RSPI detects an SSLA0 input signal negation from the beginning
of serial transfer to the end of serial transfer (refer to
section 38.3.8, Error Detection).
The final sampling timing changes depending on the bit length of transfer data. In slave mode, the RSPI data length
depends on the SPCMD0.SPB[3:0] bit setting. The polarity of the SSLA0 input signal depends on the SSLP.SSL0P bit
setting.
For details on the RSPI transfer format, refer to
section 38.3.5, Transfer Format.
(3) Notes on Single-Slave Operations
If the SPCMD0.CPHA bit is 0, the RSPI starts serial transfers when it detects the assertion edge for an SSLA0 input
signal. In the type of configuration shown in
Figure 38.7 as an example, if the RSPI is used in single-slave mode, the
SSLA0 signal is fixed at the active state. Therefore, when the CPHA bit is set to 0, the RSPI cannot correctly start a serial
transfer. To correctly execute transmit/receive operations by the RSPI in slave mode in a configuration in which the
SSLA0 input signal is fixed at the active state, the CPHA bit should be set to 1. If there is a need for setting the CPHA bit
to 0, the SSLA0 input signal should not be fixed.