Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1390 of 1852
Nov 30, 2020
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.3.8.1 Overrun Error
If a serial transfer ends when the receive buffer of SPDR is full, the RSPI detects an overrun error, and sets the
SPSR.OVRF flag to 1. When the OVRF flag is 1, the RSPI does not copy data from the shift register to the receive buffer
so that the data prior to the occurrence of the error is retained in the receive buffer. To set the OVRF flag to 0, write 0 to
the OVRF flag after the CPU has read SPSR with the OVRF flag set to 1.
Figure 38.27 shows an example of operations of the SPRF and OVRF flags. The SPSR and SPDR accesses shown in
Figure 38.27 indicate the condition of accesses to SPSR and SPDR, respectively, where W denotes a write cycle, and R
a read cycle. In the example in
Figure 38.27, the RSPI performs an 8-bit serial transfer in which the SPCMDm.CPHA
bit is 1 and the SPCMDm.CPOL bit is 0. The numbers given under the RSPCKA waveform represent the number of
RSPCK cycles (i.e., the number of transferred bits).
Figure 38.27 Operation Example of SPRF and OVRF Flags
The operation of the flags at the timing shown in steps (1) to (4) in the figure is described below.
(1) If a serial transfer terminates with the receive buffer full (the SPRF flag is 1), the RSPI detects an overrun error, and
sets the OVRF flag to 1. The RSPI does not copy the data in the shift register to the receive buffer. Even if the SPPE
bit is 1, parity errors are not detected. In master mode, the RSPI copies the pointer value to SPCMDm register to the
SPSSR.SPECM[2:0] bits.
(2) When SPDR is read, the RSPI outputs the data in the receive buffer. At this time the SPRF flag becomes 0. Even if
the receive buffer becomes empty, the OVRF flag does not become 0.
(3) If the serial transfer ends with the OVRF flag being 1 (an overrun error occurs), the RSPI does not copy the data in
the shift register to the receive buffer (the SPRF flag remains 0). A receive buffer full interrupt is not generated.
Even if the SPPE bit is 1, parity errors are not detected. When in master mode, the RSPI does not update the
SPSSR.SPECM[2:0] bits. When in an overrun error state and the RSPI does not copy the received data from the
shift register to the receive buffer, upon termination of the serial transfer, the RSPI determines that the shift register
is empty; in this manner, data transfer from the transmit buffer to the shift register is enabled.
(4) If 0 is written to the OVRF flag after SPSR is read when the OVRF flag is 1, the OVRF flag is set to 0.
The occurrence of an overrun can be checked either by reading SPSR or by using an RSPI error interrupt and reading
SPSR. When executing a serial transfer, measures should be taken to ensure the early detection of overrun errors, such as
reading SPSR immediately after SPDR is read. When the RSPI is used in master mode, the pointer value to SPCMDm
register at the occurrence of the error can be checked by reading the SPSSR.SPECM[2:0] bits.
If an overrun error occurs and the OVRF flag is set to 1, normal reception operations cannot be performed until the
OVRF flag is set to 0.
R
87654321 87654321
R W
Full Empty
(3)
(1)
(2)
(4)
SPDR access
SPSR access
Receive buffer status
OVRF
SPRF
RSPCKA
(CPHA = 1, CPOL = 0)