Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1387 of 1852
Nov 30, 2020
RX23W Group 38. Serial Peripheral Interface (RSPIa)
38.3.7 Transmit Buffer Empty/Receive Buffer Full Interrupts
Figure 38.26 shows an example of operation of the transmit buffer empty interrupt (SPTI) and the receive buffer full
interrupt (SPRI). The SPDR register access shown in
Figure 38.26 indicates the condition of access to the SPDR
register, where W denotes a write cycle, and R a read cycle. In the example in
Figure 38.26, the RSPI performs an 8-bit
serial transfer in which the SPCR.TXMD bit is 0, the SPDCR.SPFC[1:0] bits are 00b, the SPCMDm.CPHA bit is 1, and
the SPCMDm.CPOL bit is 0. The numbers given under the RSPCKA waveform represent the number of RSPCK cycles
(i.e., the number of transferred bits).
Figure 38.26 Operation Example of SPTI and SPRI Interrupts
The operation of the interrupts at timings shown in steps (1) to (5) in the figure is described below.
(1) When transmit data is written to SPDR when the transmit buffer of SPDR is empty (data for the next transfer is not
set), the RSPI writes data to the transmit buffer and sets the SPSR.SPTEF flag to 0.
(2) If the shift register is empty, the RSPI copies the data from the transmit buffer to the shift register and generates a
transmit buffer empty interrupt request (SPTI) and sets the SPSR.SPTEF flag to 1. How a serial transfer is started
depends on the mode of the RSPI. For details, refer to
section 38.3.10, SPI Operation, and section 38.3.11,
Clock Synchronous Operation
.
(3) When transmit data is written to SPDR in the transmit buffer empty interrupt routine or in the transmit buffer empty
detecting process by polling the SPTEF flag, the data is transferred to the transmit buffer and the SPSR.SPTEF flag
becomes 0. Because the data being transmitted is stored in the shift register, the RSPI does not copy the data from
the transmit buffer to the shift register.
(4) When the serial transfer ends with the receive buffer of SPDR being empty, the RSPI copies the receive data from
the shift register to the receive buffer, generates a receive buffer full interrupt request (SPRI), and sets the
SPSR.SPRF flag to 1. Since the shift register becomes empty upon completion of serial transfer, when the transmit
buffer had been full before the serial transfer ended, the RSPI sets the SPSR.SPTEF flag to 1 and copies the data
from the transmit buffer to the shift register. Even when received data is not copied from the shift register to the
receive buffer in an overrun error status, upon completion of the serial transfer, the RSPI determines that the shift
register is empty, thus data transfer from the transmit buffer to the shift register is enabled.
W W
SPDR access
(3)
(2)
(1)
R
87654321 87654321
Empty
Full Empty
Empty
Full
Empty
Full
Transmit buffer status
Receive buffer status
SPTI
SPRI
(4)
(5)
SPTEF
SPRF
Empty Full
(CPHA = 1, CPOL = 0)
RSPCKA