Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1314 of 1852
Nov 30, 2020
RX23W Group 37. Serial Sound Interface (SSI)
REN Bit (Receive Enable)
This bit enables or disables receive operation. Setting this bit to 1 starts receive operation.
TEN Bit (Transmit Enable)
This bit enables or disables transmit operation. Setting this bit to 1 starts transmit operation.
SSITXD0 pin of SSI0 is set as output while SSITXD0 is selected by the multi-function pin controller (MPC), regardless
of the TEN bit setting.
x: Don't care
—: Settings prohibited.
CKDV[3:0] Bits (Serial Bit Clock Frequency Setting)
These bits select the frequency of the serial bit clock in master mode. Since the input clock from the SSISCK0 pin is used
in slave mode, the setting of these bits is ignored. The serial bit clock is used as the operating clock of the shift register.
Calculation Example:
When fs (sampling rate) = the SSIWS0 frequency = 96 kHz and the system word length = 32 bits
The bit clock frequency = 96 kHz × 32 bits × 2 = 6.144 MHz is necessary, so set CKDV[3:0] = 0001b (MCLK/2) when
MCLK = 12.288 MHz.
PDTA Bit (Parallel Data Allocation)
The setting of this bit specifies the allocation of data to be stored in the SSIFRDR register in receive mode and the
SSIFTDR register in transmit mode.
During receive operation, the SSI stores the data received from the serial bus in the SSIFRDR register according to the
PDTA bit setting.
During transmit operation, the SSI stores the data stored in the SSIFTDR register in the transmit shift register, and
transmits the data to the serial bus according to the PDTA bit setting.
Table 37.3 SSITXD0 and SSIRXD0 Pin States
Register Settings SSI0
MPC setting TEN REN SSITXD0 SSIRXD0
SSI function 0 0 Output Input
0 1 Output Input
1 0 Output Input
1 1 Output Input
Other than SSI function x x Depends on the
selected function
Depends on the
selected function