Users Manual
Table Of Contents
- 45. 12-Bit D/A Converter (R12DAA)
- 46. Temperature Sensor (TEMPSA)
- 47. Comparator B (CMPBa)
- 47.1 Overview
- 47.2 Register Descriptions
- 47.2.1 Comparator B1 Control Register 1 (CPB1CNT1)
- 47.2.2 Comparator B1 Control Register 2 (CPB1CNT2)
- 47.2.3 Comparator B1 Flag Register (CPB1FLG)
- 47.2.4 Comparator B1 Interrupt Control Register (CPB1INT)
- 47.2.5 Comparator B1 Filter Select Register (CPB1F)
- 47.2.6 Comparator B1 Mode Select Register (CPB1MD)
- 47.2.7 Comparator B1 Reference Input Voltage Select Register (CPB1REF)
- 47.2.8 Comparator B1 Output Control Register (CPB1OCR)
- 47.3 Operation
- 47.4 Comparator B2 and Comparator B3 Interrupts
- 47.5 Usage Note
- 48. Data Operation Circuit (DOC)
- 49. RAM
- 50. Flash Memory (FLASH)
- 50.1 Overview
- 50.2 ROM Area and Block Configuration
- 50.3 E2 DataFlash Area and Block Configuration
- 50.4 Register Descriptions
- 50.4.1 E2 DataFlash Control Register (DFLCTL)
- 50.4.2 Flash P/E Mode Entry Register (FENTRYR)
- 50.4.3 Protection Unlock Register (FPR)
- 50.4.4 Protection Unlock Status Register (FPSR)
- 50.4.5 Flash P/E Mode Control Register (FPMCR)
- 50.4.6 Flash Initial Setting Register (FISR)
- 50.4.7 Flash Reset Register (FRESETR)
- 50.4.8 Flash Area Select Register (FASR)
- 50.4.9 Flash Control Register (FCR)
- 50.4.10 Flash Extra Area Control Register (FEXCR)
- 50.4.11 Flash Processing Start Address Register H (FSARH)
- 50.4.12 Flash Processing Start Address Register L (FSARL)
- 50.4.13 Flash Processing End Address Register H (FEARH)
- 50.4.14 Flash Processing End Address Register L (FEARL)
- 50.4.15 Flash Write Buffer Register n (FWBn) (n = 0 to 3)
- 50.4.16 Flash Status Register 0 (FSTATR0)
- 50.4.17 Flash Status Register 1 (FSTATR1)
- 50.4.18 Flash Error Address Monitor Register H (FEAMH)
- 50.4.19 Flash Error Address Monitor Register L (FEAML)
- 50.4.20 Flash Start-Up Setting Monitor Register (FSCMR)
- 50.4.21 Flash Access Window Start Address Monitor Register (FAWSMR)
- 50.4.22 Flash Access Window End Address Monitor Register (FAWEMR)
- 50.4.23 Unique ID Register n (UIDRn) (n = 0 to 3)
- 50.5 Start-Up Program Protection
- 50.6 Area Protection
- 50.7 Programming and Erasure
- 50.8 Boot Mode
- 50.9 Flash Memory Protection
- 50.10 Communication Protocol
- 50.10.1 State Transition in Boot Mode (SCI Interface)
- 50.10.2 Command and Response Configuration
- 50.10.3 Response to Undefined Commands
- 50.10.4 Boot Mode Status Inquiry
- 50.10.5 Inquiry Commands
- 50.10.6 Setting Commands
- 50.10.7 ID Code Authentication Command
- 50.10.8 Program/Erase Commands
- 50.10.9 Read-Check Commands
- 50.11 Serial Programmer Operation in Boot Mode (SCI Interface)
- 50.11.1 Bit Rate Automatic Adjustment Procedure
- 50.11.2 Procedure to Receive the MCU Information
- 50.11.3 Procedure to Select the Device and Change the Bit Rate
- 50.11.4 Procedure for Transition to the Program/Erase Host Command Wait State
- 50.11.5 Procedure to Unlock Boot Mode ID Code Protection
- 50.11.6 Procedure to Erase the User Area and Data Area
- 50.11.7 Procedure to Program the User Area and Data Area
- 50.11.8 Procedure to Check Data in the User Area
- 50.11.9 Procedure to Check Data in the Data Area
- 50.11.10 Procedure to Set the Access Window in the User Area
- 50.12 Rewriting by Self-Programming
- 50.13 Usage Notes
- 50.14 Usage Notes in Boot Mode
- 51. Electrical Characteristics
- 51.1 Absolute Maximum Ratings
- 51.2 DC Characteristics
- 51.3 AC Characteristics
- 51.3.1 Clock Timing
- 51.3.2 Reset Timing
- 51.3.3 Timing of Recovery from Low Power Consumption Modes
- 51.3.4 Control Signal Timing
- 51.3.5 Timing of On-Chip Peripheral Modules
- 51.3.5.1 Timing of I/O Ports
- 51.3.5.2 Timing of MTU/TPU
- 51.3.5.3 Timing of POE
- 51.3.5.4 Timing of TMR
- 51.3.5.5 Timing of SCI
- 51.3.5.6 Timing of RIIC
- 51.3.5.7 Timing of RSPI
- 51.3.5.8 Timing of SSI
- 51.3.5.9 Timing of SDHI
- 51.3.5.10 Timing of A/D Converter Trigger
- 51.3.5.11 Timing of CAC
- 51.3.5.12 Timing of CLKOUT
- 51.3.5.13 Timing of CLKOUT_RF
- 51.4 USB Characteristics
- 51.5 A/D Conversion Characteristics
- 51.6 D/A Conversion Characteristics
- 51.7 Temperature Sensor Characteristics
- 51.8 Comparator Characteristics
- 51.9 CTSU Characteristics
- 51.10 Characteristics of Power-On Reset Circuit and Voltage Detection Circuit
- 51.11 Oscillation Stop Detection Timing
- 51.12 Battery Backup Function Characteristics
- 51.13 ROM (Flash Memory for Code Storage) Characteristics
- 51.14 E2 DataFlash Characteristics (Flash Memory for Data Storage)
- 51.15 BLE Characteristics
- 51.16 Usage Notes
- Appendix 1. Port States in Each Processing Mode
- Appendix 2. Package Dimensions
- REVISION HISTORY
- Colophon
- Address List
- Back cover
R01UH0823EJ0110 Rev.1.10 Page 1624 of 1852
Nov 30, 2020
RX23W Group 44. 12-Bit A/D Converter (S12ADE)
44.3.5.3 Using Data Buffers
This S12ADE is provided with a ring buffer function consisting of 16 A/D data buffers. This function sequentially stores
A/D conversion results other than self-diagnosis result (including addition/average results) in data buffers (ADBUFn, n =
0 to 15) when the compare function is used.
Each conversion result is stored at the timing when the A/D conversion result is stored in the data register, and most
recent 16 conversion result data are retained.
The following shows the schematic of data buffers, pointer, and overflow flag operations. When the BUFEN bit is set
to1, the A/D conversion result is transferred at each end of A/D conversion. The pointer indicates the number of data
buffer to which the next transferred data is to be written. When data is written to up to buffer 15, the pointer is reset to
0000b and the overflow flag is set to 1. Subsequently transferred data overwrites the previously written data. The pointer
and overflow flag are reset to the initial value by writing 00h to the ADBUFPTR register.
Figure 44.21 Schematic of Data Buffers, Pointer, and Overflow Flag Operations
BUF_0
BUF_1
BUF_2
BUF_14
BUF_15
BUFPTR
After reset
= 0000b = 000h
= 000h
= 000h
= 000h
= 000h
After 1-time conversion
= 0001b
= aaah
= 000h
= 000h
= 000h
= 000h
PTROVF = 0
After 2-time conversion
= 0010b
= aaah
= bbbh
= 000h
= 000h
= 000h
After 15-time conversion
= 1111b
= aaah
= bbbh
= ccch
= adch
= 000h
After 16-time conversion
= 0000b = aaah
= bbbh
= ccch
= adch
= defh
After 17-time conversion
= 0001b
= 111h
= bbbh
= ccch
= adch
= defh
Data is overwritten
Write ADBUFPTR = 00h
= 0000b = 111h
= bbbh
= ccch
= adch
= defh
:
:
Pointer continues operating
BUF_0
BUF_1
BUF_2
BUF_14
BUF_15
BUFPTR
PTROVF = 0
:
:
BUF_0
BUF_1
BUF_2
BUF_14
BUF_15
BUFPTR
PTROVF = 0
:
:
BUF_0
BUF_1
BUF_2
BUF_14
BUF_15
BUFPTR
PTROVF = 0
:
:
BUF_0
BUF_1
BUF_2
BUF_14
BUF_15
BUFPTR
PTROVF = 1
:
:
BUF_0
BUF_1
BUF_2
BUF_14
BUF_15
BUFPTR
PTROVF = 1
:
:
BUF_0
BUF_1
BUF_2
BUF_14
BUF_15
BUFPTR
PTROVF = 0
:
: