Users Manual
Table Of Contents
- 45. 12-Bit D/A Converter (R12DAA)
- 46. Temperature Sensor (TEMPSA)
- 47. Comparator B (CMPBa)
- 47.1 Overview
- 47.2 Register Descriptions
- 47.2.1 Comparator B1 Control Register 1 (CPB1CNT1)
- 47.2.2 Comparator B1 Control Register 2 (CPB1CNT2)
- 47.2.3 Comparator B1 Flag Register (CPB1FLG)
- 47.2.4 Comparator B1 Interrupt Control Register (CPB1INT)
- 47.2.5 Comparator B1 Filter Select Register (CPB1F)
- 47.2.6 Comparator B1 Mode Select Register (CPB1MD)
- 47.2.7 Comparator B1 Reference Input Voltage Select Register (CPB1REF)
- 47.2.8 Comparator B1 Output Control Register (CPB1OCR)
- 47.3 Operation
- 47.4 Comparator B2 and Comparator B3 Interrupts
- 47.5 Usage Note
- 48. Data Operation Circuit (DOC)
- 49. RAM
- 50. Flash Memory (FLASH)
- 50.1 Overview
- 50.2 ROM Area and Block Configuration
- 50.3 E2 DataFlash Area and Block Configuration
- 50.4 Register Descriptions
- 50.4.1 E2 DataFlash Control Register (DFLCTL)
- 50.4.2 Flash P/E Mode Entry Register (FENTRYR)
- 50.4.3 Protection Unlock Register (FPR)
- 50.4.4 Protection Unlock Status Register (FPSR)
- 50.4.5 Flash P/E Mode Control Register (FPMCR)
- 50.4.6 Flash Initial Setting Register (FISR)
- 50.4.7 Flash Reset Register (FRESETR)
- 50.4.8 Flash Area Select Register (FASR)
- 50.4.9 Flash Control Register (FCR)
- 50.4.10 Flash Extra Area Control Register (FEXCR)
- 50.4.11 Flash Processing Start Address Register H (FSARH)
- 50.4.12 Flash Processing Start Address Register L (FSARL)
- 50.4.13 Flash Processing End Address Register H (FEARH)
- 50.4.14 Flash Processing End Address Register L (FEARL)
- 50.4.15 Flash Write Buffer Register n (FWBn) (n = 0 to 3)
- 50.4.16 Flash Status Register 0 (FSTATR0)
- 50.4.17 Flash Status Register 1 (FSTATR1)
- 50.4.18 Flash Error Address Monitor Register H (FEAMH)
- 50.4.19 Flash Error Address Monitor Register L (FEAML)
- 50.4.20 Flash Start-Up Setting Monitor Register (FSCMR)
- 50.4.21 Flash Access Window Start Address Monitor Register (FAWSMR)
- 50.4.22 Flash Access Window End Address Monitor Register (FAWEMR)
- 50.4.23 Unique ID Register n (UIDRn) (n = 0 to 3)
- 50.5 Start-Up Program Protection
- 50.6 Area Protection
- 50.7 Programming and Erasure
- 50.8 Boot Mode
- 50.9 Flash Memory Protection
- 50.10 Communication Protocol
- 50.10.1 State Transition in Boot Mode (SCI Interface)
- 50.10.2 Command and Response Configuration
- 50.10.3 Response to Undefined Commands
- 50.10.4 Boot Mode Status Inquiry
- 50.10.5 Inquiry Commands
- 50.10.6 Setting Commands
- 50.10.7 ID Code Authentication Command
- 50.10.8 Program/Erase Commands
- 50.10.9 Read-Check Commands
- 50.11 Serial Programmer Operation in Boot Mode (SCI Interface)
- 50.11.1 Bit Rate Automatic Adjustment Procedure
- 50.11.2 Procedure to Receive the MCU Information
- 50.11.3 Procedure to Select the Device and Change the Bit Rate
- 50.11.4 Procedure for Transition to the Program/Erase Host Command Wait State
- 50.11.5 Procedure to Unlock Boot Mode ID Code Protection
- 50.11.6 Procedure to Erase the User Area and Data Area
- 50.11.7 Procedure to Program the User Area and Data Area
- 50.11.8 Procedure to Check Data in the User Area
- 50.11.9 Procedure to Check Data in the Data Area
- 50.11.10 Procedure to Set the Access Window in the User Area
- 50.12 Rewriting by Self-Programming
- 50.13 Usage Notes
- 50.14 Usage Notes in Boot Mode
- 51. Electrical Characteristics
- 51.1 Absolute Maximum Ratings
- 51.2 DC Characteristics
- 51.3 AC Characteristics
- 51.3.1 Clock Timing
- 51.3.2 Reset Timing
- 51.3.3 Timing of Recovery from Low Power Consumption Modes
- 51.3.4 Control Signal Timing
- 51.3.5 Timing of On-Chip Peripheral Modules
- 51.3.5.1 Timing of I/O Ports
- 51.3.5.2 Timing of MTU/TPU
- 51.3.5.3 Timing of POE
- 51.3.5.4 Timing of TMR
- 51.3.5.5 Timing of SCI
- 51.3.5.6 Timing of RIIC
- 51.3.5.7 Timing of RSPI
- 51.3.5.8 Timing of SSI
- 51.3.5.9 Timing of SDHI
- 51.3.5.10 Timing of A/D Converter Trigger
- 51.3.5.11 Timing of CAC
- 51.3.5.12 Timing of CLKOUT
- 51.3.5.13 Timing of CLKOUT_RF
- 51.4 USB Characteristics
- 51.5 A/D Conversion Characteristics
- 51.6 D/A Conversion Characteristics
- 51.7 Temperature Sensor Characteristics
- 51.8 Comparator Characteristics
- 51.9 CTSU Characteristics
- 51.10 Characteristics of Power-On Reset Circuit and Voltage Detection Circuit
- 51.11 Oscillation Stop Detection Timing
- 51.12 Battery Backup Function Characteristics
- 51.13 ROM (Flash Memory for Code Storage) Characteristics
- 51.14 E2 DataFlash Characteristics (Flash Memory for Data Storage)
- 51.15 BLE Characteristics
- 51.16 Usage Notes
- Appendix 1. Port States in Each Processing Mode
- Appendix 2. Package Dimensions
- REVISION HISTORY
- Colophon
- Address List
- Back cover
R01UH0823EJ0110 Rev.1.10 Page 1847 of 1852
Nov 30, 2020
RX23W Group REVISION HISTORY
1.10 Nov 30, 2020 952 32.3.7 Bulk Transfers (Pipes 1 to 5), changed
952 32.3.8 Interrupt Transfers (Pipes 6 to 9), title changed
953 32.3.9 Isochronous Transfers (Pipes 1 and 2), title changed
962 32.3.11.2 Transfer Schedule, changed
963 32.4.1 Setting the Module-Stop Function, changed
33. Serial Communications Interface (SCIg, SCIh)
971 Table 33.2 SCIh Specifications (2/2), changed
985, 986 33.2.8 Serial Control Register (SCR)
(1) Non-Smart Card Interface Mode (SCMR.SMIF = 0), changed
994, 995 33.2.10 Smart Card Mode Register (SCMR), changed
1028 33.3.2 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode, Note 1, changed
1031, 1032 33.3.6 SCI Initialization (Asynchronous Mode), changed
1031 Figure 33.8 Sample SCI Initialization Flowchart (Asynchronous Mode),
changed
1037 to 1040 33.3.8 Serial Data Reception (Asynchronous Mode), changed
1038 Table 33.28 Status Flags in the SSR Register and Receive Data Handling,
changed
1047 33.5.2 CTS and RTS Functions, changed
1048 33.5.3 SCI Initialization (Clock Synchronous Mode), changed
1048 Figure 33.24 Example of SCI Initialization Flowchart (Clock Synchronous
Mode), changed
1053 to 1055 33.5.5 Serial Data Reception (Clock Synchronous Mode), changed
1055 Figure 33.31 Example Flowchart of Serial Reception in Clock Synchronous
Mode, changed
1056 Figure 33.32 Example Flowchart of Simultaneous Serial Transmission and
Reception in Clock Synchronous Mode, changed
1060 33.6.3 Block Transfer Mode, changed
1061 Figure 33.38 Example of SCI Initialization Flowchart (Smart Card Interface
Mode), changed
1063 to 1065 33.6.6 Serial Data Transmission (Except in Block Transfer Mode), changed
1066, 1067 33.6.7 Serial Data Reception (Except in Block Transfer Mode), changed
1074 Figure 33.51 Example of the Flowchart of SCI Initialization (for Simple I
2
C
Mode), changed
1076 Figure 33.54 Example of the Procedure for Master Transmission
Operations in Simple I
2
C Mode (with Transmission Interrupts and
Reception Interrupts in Use), changed
1083 33.8.5 SCI Initialization (Simple SPI Mode), changed
1100 Figure 33.75 Block Diagram of Digital Noise Filter, title changed
1101 33.12.2 Interrupts in Asynchronous Mode, Clock Synchronous Mode, and
Simple SPI Mode, changed
1113 Figure 33.82 Example of Flowchart for Receive Error Handling (during
Reception of the Start Frame), changed
35. I
2
C-bus Interface (RIICa)
1121 to 1123 35.1 Overview, changed
1121 Table 35.1 RIIC Specifications (1/2), changed
1122 Table 35.1 RIIC Specifications (2/2), changed
1122 Figure 35.1 RIIC Block Diagram, changed
1123 Figure 35.2 I/O Pin Connection to the External Circuit (I
2
C-bus
Configuration Example), changed
1124, 1125 35.2.1 I
2
C-bus Control Register 1 (ICCR1), changed
1126 to 1129 35.2.2 I
2
C-bus Control Register 2 (ICCR2), changed
1130 35.2.3 I
2
C-bus Mode Register 1 (ICMR1), changed
1131, 1132 35.2.4 I
2
C-bus Mode Register 2 (ICMR2), changed
1133, 1134 35.2.5 I
2
C-bus Mode Register 3 (ICMR3), changed
1135, 1136 35.2.6 I
2
C-bus Function Enable Register (ICFER), changed TN-RX*-A0227A/E
1141 to 1143 35.2.9 I
2
C-bus Status Register 1 (ICSR1), changed
1144 to 1146 35.2.10 I
2
C-bus Status Register 2 (ICSR2), changed TN-RX*-A0227A/E
1145 Table 35.4 Relationship between Arbitration-Lost Generation Sources and
Arbitration-Lost Enable Functions, changed
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