Users Manual
Table Of Contents
- 45. 12-Bit D/A Converter (R12DAA)
- 46. Temperature Sensor (TEMPSA)
- 47. Comparator B (CMPBa)
- 47.1 Overview
- 47.2 Register Descriptions
- 47.2.1 Comparator B1 Control Register 1 (CPB1CNT1)
- 47.2.2 Comparator B1 Control Register 2 (CPB1CNT2)
- 47.2.3 Comparator B1 Flag Register (CPB1FLG)
- 47.2.4 Comparator B1 Interrupt Control Register (CPB1INT)
- 47.2.5 Comparator B1 Filter Select Register (CPB1F)
- 47.2.6 Comparator B1 Mode Select Register (CPB1MD)
- 47.2.7 Comparator B1 Reference Input Voltage Select Register (CPB1REF)
- 47.2.8 Comparator B1 Output Control Register (CPB1OCR)
- 47.3 Operation
- 47.4 Comparator B2 and Comparator B3 Interrupts
- 47.5 Usage Note
- 48. Data Operation Circuit (DOC)
- 49. RAM
- 50. Flash Memory (FLASH)
- 50.1 Overview
- 50.2 ROM Area and Block Configuration
- 50.3 E2 DataFlash Area and Block Configuration
- 50.4 Register Descriptions
- 50.4.1 E2 DataFlash Control Register (DFLCTL)
- 50.4.2 Flash P/E Mode Entry Register (FENTRYR)
- 50.4.3 Protection Unlock Register (FPR)
- 50.4.4 Protection Unlock Status Register (FPSR)
- 50.4.5 Flash P/E Mode Control Register (FPMCR)
- 50.4.6 Flash Initial Setting Register (FISR)
- 50.4.7 Flash Reset Register (FRESETR)
- 50.4.8 Flash Area Select Register (FASR)
- 50.4.9 Flash Control Register (FCR)
- 50.4.10 Flash Extra Area Control Register (FEXCR)
- 50.4.11 Flash Processing Start Address Register H (FSARH)
- 50.4.12 Flash Processing Start Address Register L (FSARL)
- 50.4.13 Flash Processing End Address Register H (FEARH)
- 50.4.14 Flash Processing End Address Register L (FEARL)
- 50.4.15 Flash Write Buffer Register n (FWBn) (n = 0 to 3)
- 50.4.16 Flash Status Register 0 (FSTATR0)
- 50.4.17 Flash Status Register 1 (FSTATR1)
- 50.4.18 Flash Error Address Monitor Register H (FEAMH)
- 50.4.19 Flash Error Address Monitor Register L (FEAML)
- 50.4.20 Flash Start-Up Setting Monitor Register (FSCMR)
- 50.4.21 Flash Access Window Start Address Monitor Register (FAWSMR)
- 50.4.22 Flash Access Window End Address Monitor Register (FAWEMR)
- 50.4.23 Unique ID Register n (UIDRn) (n = 0 to 3)
- 50.5 Start-Up Program Protection
- 50.6 Area Protection
- 50.7 Programming and Erasure
- 50.8 Boot Mode
- 50.9 Flash Memory Protection
- 50.10 Communication Protocol
- 50.10.1 State Transition in Boot Mode (SCI Interface)
- 50.10.2 Command and Response Configuration
- 50.10.3 Response to Undefined Commands
- 50.10.4 Boot Mode Status Inquiry
- 50.10.5 Inquiry Commands
- 50.10.6 Setting Commands
- 50.10.7 ID Code Authentication Command
- 50.10.8 Program/Erase Commands
- 50.10.9 Read-Check Commands
- 50.11 Serial Programmer Operation in Boot Mode (SCI Interface)
- 50.11.1 Bit Rate Automatic Adjustment Procedure
- 50.11.2 Procedure to Receive the MCU Information
- 50.11.3 Procedure to Select the Device and Change the Bit Rate
- 50.11.4 Procedure for Transition to the Program/Erase Host Command Wait State
- 50.11.5 Procedure to Unlock Boot Mode ID Code Protection
- 50.11.6 Procedure to Erase the User Area and Data Area
- 50.11.7 Procedure to Program the User Area and Data Area
- 50.11.8 Procedure to Check Data in the User Area
- 50.11.9 Procedure to Check Data in the Data Area
- 50.11.10 Procedure to Set the Access Window in the User Area
- 50.12 Rewriting by Self-Programming
- 50.13 Usage Notes
- 50.14 Usage Notes in Boot Mode
- 51. Electrical Characteristics
- 51.1 Absolute Maximum Ratings
- 51.2 DC Characteristics
- 51.3 AC Characteristics
- 51.3.1 Clock Timing
- 51.3.2 Reset Timing
- 51.3.3 Timing of Recovery from Low Power Consumption Modes
- 51.3.4 Control Signal Timing
- 51.3.5 Timing of On-Chip Peripheral Modules
- 51.3.5.1 Timing of I/O Ports
- 51.3.5.2 Timing of MTU/TPU
- 51.3.5.3 Timing of POE
- 51.3.5.4 Timing of TMR
- 51.3.5.5 Timing of SCI
- 51.3.5.6 Timing of RIIC
- 51.3.5.7 Timing of RSPI
- 51.3.5.8 Timing of SSI
- 51.3.5.9 Timing of SDHI
- 51.3.5.10 Timing of A/D Converter Trigger
- 51.3.5.11 Timing of CAC
- 51.3.5.12 Timing of CLKOUT
- 51.3.5.13 Timing of CLKOUT_RF
- 51.4 USB Characteristics
- 51.5 A/D Conversion Characteristics
- 51.6 D/A Conversion Characteristics
- 51.7 Temperature Sensor Characteristics
- 51.8 Comparator Characteristics
- 51.9 CTSU Characteristics
- 51.10 Characteristics of Power-On Reset Circuit and Voltage Detection Circuit
- 51.11 Oscillation Stop Detection Timing
- 51.12 Battery Backup Function Characteristics
- 51.13 ROM (Flash Memory for Code Storage) Characteristics
- 51.14 E2 DataFlash Characteristics (Flash Memory for Data Storage)
- 51.15 BLE Characteristics
- 51.16 Usage Notes
- Appendix 1. Port States in Each Processing Mode
- Appendix 2. Package Dimensions
- REVISION HISTORY
- Colophon
- Address List
- Back cover
R01UH0823EJ0110 Rev.1.10 Page 1845 of 1852
Nov 30, 2020
RX23W Group REVISION HISTORY
Classifications
- Items with Technical Update document number: Changes according to the corresponding issued Technical Update
- Items without Technical Update document number: Minor changes that do not require Technical Update to be issued
REVISION HISTORY RX23W Group User’s Manual: Hardware
Rev. Date
Description
Classification
Page Summary
1.00 Jul 31, 2019 — First edition, issued
1.10 Nov 30, 2020 Features
51 83-pin LGA specifications, added
1. Overview
All 83-pin LGA specifications, added
9. Clock Generation Circuit
173, 174 Table 9.1 Specifications of Clock Generation Circuit, changed
176 Figure 9.2 Block Diagram of Clock Generation Circuit (83-Pin LGA), added
206 9.5 Dedicated Clock Oscillator for Bluetooth, changed
206 9.5.1 Connecting the Oscillator, added
206 Figure 9.11 Example of the Connection of a 32-MHz Crystal Resonator,
changed
207 Figure 9.12 Example of Connection of the Bluetooth-dedicated clock output
pin, added
212 9.9.2 Note on Rewriting the SCKCR3 Register, added TN-RX*-A0224B/E
19. Data Transfer Controller (DTCa)
394 19.2.8 DTC Vector Base Register (DTCVBR), changed
20. Event Link Controller (ELC)
421 Table 20.3 Correspondence between Values Set in ELSRn.ELS[7:0] Bits
and Event Signals (1/2), changed
424 20.2.5 Event Link Option Setting Register C (ELOPC), changed
431 Table 20.5 Operations of Peripheral Modules When Event Signal is Input,
changed
432 20.3.4 Operation of CTSU When Event Signal is Input, added
22. Multi-Function Pin Controller (MPC)
All 83-pin LGA specifications, added
28. Realtime Clock (RTCe)
789, 790 28.2.18 RTC Control Register 2 (RCR2), changed
793, 794 28.2.21 Time Capture Control Register n (RTCCRn) (n = 0, 1), changed
801 Figure 28.3 Clock and Count Mode Setting Procedure, changed
802 Figure 28.4 Setting the Time, changed
802 Figure 28.5 30-Second Adjustment, changed
808 28.3.9 Time Capture Function, title changed
813 28.6.5 Notes on Writing to and Reading from Registers, title changed
814 Figure 28.14 Initialization Procedure, changed
29. Low-Power Timer (LPT)
815 Table 29.1 LPT Specifications, changed
815 Figure 29.1 LPT Block Diagram, changed
816, 817 29.2.1 Low-Power Timer Control Register 1 (LPTCR1), changed
818 29.2.3 Low-Power Timer Control Register 3 (LPTCR3), changed
819 29.2.4 Low-Power Timer Period Setting Register (LPTPRD), changed
820 Table 29.2 Example of Low-Power Timer Period Settings for IWDTCLK,
changed
821 Table 29.3 Example of Low-Power Timer Period Settings for Sub-Clock,
changed
822 29.2.5 Low-Power Timer Compare Register 0 (LPCMR0), changed
823 29.2.6 Low-Power Timer Standby Wakeup Enable Register (LPWUCR),
changed
824, 825 29.3.1 Periodic Counting Operation, changed
827 29.4 Wakeup from Software Standby Mode by an Interrupt through the
Event Link Controller (ELC), changed
REVISION HISTORY