Users Manual

R01UH0823EJ0110 Rev.1.10 Page 1798 of 1852
Nov 30, 2020
RX23W Group 51. Electrical Characteristics
51.3.5.5 Timing of SCI
Note 1. t
Pcyc
: PCLK cycle
Figure 51.39 SCK Clock Input Timing
Table 51.36 Timing of SCI
Conditions: 1.8 V ≤ VCC = VCC_USB = AVCC0 = VCC_RF = AVCC_RF ≤ 3.6 V, VSS = AVSS0 = VSS_USB = VSS_RF = 0 V,
T
a
= –40 to +85°C
Item Symbol Min. Max.
Unit
*1
Test
Conditions
SCI Input clock cycle time Asynchronous t
Scyc
4—t
Pcyc
Figure 51.39
Clock synchronous 6 —
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rise time t
SCKr
—20ns
Input clock fall time t
SCKf
—20ns
Output clock cycle time Asynchronous t
Scyc
16 — t
Pcyc
Figure 51.40
Clock synchronous 4 —
Output clock pulse width t
SCKW
0.4 0.6 t
Scyc
Output clock rise time t
SCKr
—20ns
Output clock fall time t
SCKf
—20ns
Transmit data delay time
(master)
Clock synchronous t
TXD
—40ns
Transmit data delay time
(slave)
Clock
synchronous
2.7 V or above — 65 ns
1.8 V or above — 100 ns
Receive data setup time
(master)
Clock
synchronous
2.7 V or above t
RXS
65 — ns
1.8 V or above 90 — ns
Receive data setup time
(slave)
Clock synchronous 40 — ns
Receive data hold time Clock synchronous t
RXH
40 — ns
t
SCKW
t
SCKr
t
SCKf
t
Scyc
SCKn
n = 1, 5, 8, 12