User's Manual

Theory of Operation GMH Series VHF Radio
Page 4-2 BK RADIO
4.3 THEORY OF OPERATION
4.3.1 System board
System board functions include:
1. Core Microprocessor
2. Regulation: 5.0, 8.6, 9.6, and 20.0 Volts
3. Synthesizer
4. Squelch Detection
5. CTCSS/CDCSS Decode
6. Power Control
4.3.1.1 Microprocessor Control
The core microprocessor (U507) communicates with the control head microprocessor and controls radio
functions such as loading the synthesizer, adjusting the deviation and receiver tuning, and CTCSS/CDCSS
detection. An EEPROM is used to store calibration and tuning data unique to each radio. A 32.768 kHz
crystal is used as a clock for the core microprocessor.
Various transistors provide level interfaces and current capability.
4.3.1.2 Regulation: 5.0, 8.6, 9.6, and 20.0 Volts
U502 and associated circuitry comprise a 9.6 volt low noise feedback regulator for use by noise-sensitive
analog circuitry on the system and RX/TX boards. A low battery indication is derived by sensing the error
control voltage of this regulator.
U601 and associated circuitry provide a second level of regulation to supply the VCO and synthesizer with
8.6 volts and 5.0 volts.
U504 is the 5 volt supply for the core of the radio.
The microprocessor drives a FET amplifier (Q503) tied to a voltage doubler. This forms a 20 volt switching
regulator which is regulated by error amplifier U502 which controls the gain on the FET.
4.3.1.3 Synthesizer
Synthesizer IC - U604 forms the main synthesizer IC which contains three programmable CMOS dividers
and a sample-and–hold phase detector. The first divider (divide-by-R) divides the reference oscillator
down to a frequency which is used as a reference by the sample-and-hold phase detector. The second
divider (divide-by-N) divides the output of the Prescaler down to a frequency which is equal to the divided
down reference frequency when the loop is locked. The third divider (divide-by-A) controls the modulus
control line of the Prescaler. The sample-and-hold phase detector provides a DC voltage that is
proportional to the phase error between the divided down reference frequency and the divided down
carrier frequency. This voltage is fed through the loop filter to the VCO and adjusts the VCO frequency to
maintain phase lock between the divided down frequencies.