Data Sheet

UM7 DATASHEET

Rev. 1.6 – Released 1/10/2016

SPI COMMUNICATION

The UM7 SPI bus operates at a +3.3V logic level. The UM7 is a slave on the bus, remaining

inactive unless queried by a master device. Since the SPI bus will not always be used, bus

inputs (MOSI, SCK, SS) are pulled to +3.3V internally. This prevents noise from being registered

by the UM7 as attempts to communicate with the sensor.

The UM7 SPI clock (SCK) is active high, with data clocked in on the first rising edge (usually

labeled SPI Mode 0 on microcontrollers and other devices). The master should place its data on

the MOSI line on the clock falling edge.

The maximum SPI clock rate is 10 MHz. However the UM7 needs at least 5 microseconds

between bytes to copy the next byte into the SPI transmit register. For high clock rates, this

means that a delay must be added between consecutive bytes for correct operation.

All SPI operations begin when the master writes two control bytes to the bus. The first byte

indicates whether the operation is a register read (0x00) or a write (0x01). The second byte is

the address of the register being accessed.

A read operation is performed by writing the control byte 0x00 to the MOSI line, followed by

the address of the register to be read. During the next four transfers, the UM7 will write the

contents of the register to the MISO line starting with the most-significant byte in the register

as shown in Figure 2 - Single Register Read Operation. The master should pull the MOSI line

low during the remainder of the read.

A read operation can be extended to read more than one register at a time as shown in Figure 3

- Multiple Register Read Operation to initiate the batch read, the master should write the

address of the next desired register to the MOSI line while last byte of the previous register is

being transmitted by the UM7.

A write operation is performed by writing the control byte 0x01 to the MOSI line, followed by

the address of the register to modify. During the next four transfers, the UM7 will read the

data from the MOSI line and write it to the specified register. During a write operation, the

UM7 will pull the MISO line low to indicate that it is receiving data. There is no batch write

operation. The structure of a write operation is illustrated in Figure 4 - Single Register Write

Operation.