User guide

Redpine Signals, Inc. Proprietary and Confidential. Page 94
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4.1.2 Features
 Serial interface
 Supports 8-bit and 32-bit data mode
 Supports little-endian format
4.1.3 Interrupt
The interrupt signal, an output pin of the module, is asserted when the
module needs to indicate to the host that there is data waiting to be sent
from the module to the host through the SPI interface. It is also asserted
when the module wakes up from sleep in SPI based modules. This interrupt is
active-high, level triggered.
4.1.4 Operation
The SPI interface is invoked by the Host by sending specific commands. The
descriptions that follow pertain to a Little Endian Host.
The SPI interface in the module acts as a SPI slave. Following parameters
should be in the host SPI interface.
CPOL (clock polarity) = 0,
CPHA (clock phase) = 0.
The SPI interface is programmed to perform a certain transfer using
commands C1, C2, C3 and C4 and a 32-bit address. For all the Commands
and Addresses, the Host is configured to transmit data with 8-bit mode. At
the end of all the Commands and Address, the Host is reconfigured to transfer
data with 8-bit or 32-bit mode depending on the commands issued. The Slave
responds to all the commands with a certain response pattern.
The four commands C1, C2, C3, and C4 indicate to the SPI interface all the
aspects of the transfer.
Command Type
2-bit Length
16-bit/2-bit Length Select
Master/Slave
Internal/Bus Access
Read/Write
C1 C2 C3 C4
8-bit/32-bit granularity
Internal Addr/
Misc Info
[7:6] 5 4 3 2 [1:0] [7:6] Length[7:0] Length[15:8]
Figure 15: SPI Command Description
The command description is as follows: