User guide

Redpine Signals, Inc. Proprietary and Confidential. Page 115
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confirmed that the interrupt is raised because of sleep request. If there are
packets to be sent from the host, then the Host should first mask the received
interrupt by writing a „1‟ to bit 5 of the INTR_MASK register (Base Address:
0x2200_0000, Offset Address: 0x08 ) (read back the register, set bit 5 to „1‟
and write back, so that the other bits are not changed) and then start sending
the data. If there are no packets to be sent from Host to module, then the
module can be allowed to go to sleep by writing a „1‟ to bit 5 of INTR_CLEAR
register (Base Address: 0x2200_0000, Offset Address: 0x10). After this
operation on INTR_CLEAR register, the Host should unmask the interrupt by
writing a „0‟ to bit 5 of the INTR_MASK register(read back the register, set bit 5
to „1‟ and write back, so that the other bits are not changed). This is to ensure
that the host can receive all future interrupts.
The average amount of power consumed in this mode would depend on the
DTIM period and data traffic.
If this mode is invoked when the module is not connected to an Access Point,
then the module sleeps for the time supplied in command Sleep Timer and then
wakes up.
4.6.3 Power mode 2
The RS9110-N-11-2X module powers off the Baseband and RF components in
this mode. The Core Control block interacting with the Host is always functional
in this mode. Hence, the module can receive commands from the host at any
time.
NOTE: The average current consumption in Power Mode 2 is higher than Power
Mode 1.
NOTE: While switching back to power mode 0 from power mode 1, module
resets bit 5 of Host Interrupt register automatically (to indicate it has
successfully switched back to power mode 0).