User guide

Redpine Signals, Inc. Proprietary and Confidential. Page 113
R
R
S
S
9
9
1
1
1
1
0
0
-
-
N
N
-
-
1
1
1
1
-
-
2
2
2
2
/
/
2
2
4
4
/
/
2
2
8
8
S
S
o
o
f
f
t
t
w
w
a
a
r
r
e
e
P
P
r
r
o
o
g
g
r
r
a
a
m
m
m
m
i
i
n
n
g
g
R
R
e
e
f
f
e
e
r
r
e
e
n
n
c
c
e
e
M
M
a
a
n
n
u
u
a
a
l
l
V
V
e
e
r
r
s
s
i
i
o
o
n
n
4
4
.
.
1
1
5
5
INTR_MASK
INTR_MASK
Base Address: 0x2200_0000, Offset Address: 0x08
Bit
Access
Function
Default
Value
Description
[7:6]
R
Reserved
0x3
Reserved for future use
5
R/W
POWER_M
ODE1_MAS
K
0x0
This bit is used to mask the
interrupt generated by bit 5 of
the Interrupt register. The Host
can mask this bit when it does
not want to shut down the Core
control block after the module
raises the interrupt. The Host
has to ensure that the default
values of the rest of the
register‟s bits are not
disturbed. For this, it has to
write 0xF3 to this register to
enable the mask for this
interrupt bit and 0xD3 to
disable the mask for this
interrupt bit.
[4:0]
R/W
Reserved
0x13
Reserved
Table 10: Interrupt Mask Register
The default values are set during module boot-up process.
Register Write
This is same as master write. The address to be supplied is 0x2200_0008. A
read- modify-write should be performed to write into this register so that only
the bit number 5 is written while the other bits are not changed from their
existing values.
Register Read
This is same as the master read. The address to be supplied is 0x2200_0008.