User guide

Redpine Signals, Inc. Proprietary and Confidential. Page 111
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SPI_HOST_INTR
SPI_HOST_INTR
Address: 0x00
Bit
Access
Function
Default
Value
Description
[7:0]
Read
only
SPI_HOST
_INTR
0x00
These bits indicate the interrupt vector
value coming from module side.
Bit 0: If „1‟, Buffer Full condition
reached. This bit has to be polled every
time before sending data to the
module, to check that the buffer in the
module is is full or not.
Bit 1: Reserved. Ignore this bit.
Bit 2: Reserved
Bit 3: If „1‟, indicates Data packet or
response to Management frames is
pending. This is a self-clearing interrupt
and is cleared after the packet is read
by the Host.
Bit 4: Reserved.
Bit 5: In Power Mode 1, If „1‟, indicates
that the module is awake and
requesting to shut down the Core
control block. The Host needs to write a
„1‟ to bit 5 of the INTR_CLEAR register
to clear the interrupt and also indicate
to the module that the Core control
block can be shut down.
Once the module switches from power
mode 1 to power mode 0, this bit is
automatically cleared by the module (
which indicates that the module
successfully switched back to power
mode 0)
Table 9: SPI Host Interrupt Register
Register Read
To read this register, C1 should be set to 0x41 and C3, C4 and address phases are
skipped. It is a read-only register. It can be read using the following sequence. The
C2 command bits [5:0] should be the address mentioned for this register.