User guide

Redpine Signals, Inc. Proprietary and Confidential. Page 109
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4. After sending/receiving C3, C4 commands/response, Host should wait for a
start token (0x55). The data then follows after the start token. Host writes a
dummy byte to read the data from the module each time. The Host should read
this data until the start token is received. The data following the start token
should be interpreted as the frame of specified length that is read from the
slave. Status 0x54, after C1 and C2 bytes, indicates that the device is busy. Host
has to retry. Status 0x52, after C1 and C2 bytes, indicates a failure response
from the slave.
The commands C1, C2, C3 and C4 are sent in the following sequence (explained
in Bit ordering of SPI transmission/reception) : C1 first, then C2, C3 and finally
C4. The bit ordering is
C1[7] -> C1[6] … C1[0] -> C2[7] -> C2[6] … C2[0] -> C3[7] -> C3[6] … C3[0]
-> C4[7] -> C4[6] … C4[0]. That is, C1[7] bit is sent first, then C1[6] and so on.
If <D3[7:0]> <D2[7:0]> <D1[7:0]> <D0[7:0]> is the data read, then D0 is
sent from module first, then D1 and so on.
D0[7] -> D0[6] … D0[0] -> D1[7] -> D1[6] … D1[0] -> D2[7] -> D2[6] … D2[0]
-> D3[7] -> D3[6] … D3[0]
4.5.5 Register Reads and Writes
Register Summary
Base Address: 0x0800_0000
Address Offset
Register Description
0x00
SPI_HOST_INTR
Base Address: 0x2200_0000
Address Offset
Register Description
0x04
SOFT_RESET
0x08
INTR_MASK
0x10
INTR_CLEAR
Table 7: SPI Register Description
SOFT_RESET