User's Manual

RTL8187B
Datasheet
Wireless LAN Network Interface Controller
24
Track ID: JATR-1076-21 Rev. 1.0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
S
V
D
SPC A
N
T
E
N
N
A
AGC (8 bits) RSVD
(4bits)
DELAY_BOUND (16 bits) Offset 24
FRAG_QSIZE (16 bits) E
N
_
P
M
P
D
E
N
_
B
C
K
E
Y
BCKEY (6 bits) P
T
_
E
N
T
P
C
_
E
N
TPC
_PO
LAR
ITY
T
P
C
_
D
E
S
E
N
R
S
V
D
HW
Leng
thSel
ect
Offset 28
Table 28. Tx Status Descriptor
Offset# Bit# Symbol Description
0 31 OWN Ownership.
When set, this bit indicates that the descriptor is owned by the NIC, and the
data relative to this descriptor is ready to be transmitted. When cleared, it
indicates that the descriptor is owned by the host system. The NIC clears this
bit when the relative buffer data is transmitted. In this case, OWN=1.
0 30 DMA OK DMA OK.
Set by the driver, reset by the RTL8187B when TX DMA OK. If IMR’s
corresponding bit is set and the driver sets this bit, the RTL8187B resets this
bit and issues an interrupt right after DMA OK of the last segment (LS). If not,
the RTL8187B just resets this bit without asserting an interrupt.
0 29 FS First Segment Descriptor.
When set, this bit indicates that this is the first descriptor of a Tx packet, and
that this descriptor is pointing to the first segment of the packet.
0 28 LS Last Segment Descriptor.
When set, indicates that this is the last descriptor of a Tx packet, and this
descriptor is pointing to the last segment of the packet.