Installation guide

16 Technical Overview
Receiver
Circuitw
The receiver is a complex digital signal processor. The amount and speed of data the
receiver processes rivals even the faster personal computers on the market today. The
information received from the satellite is a digital signal that is decoded and digitally
processed. There are no analog signals to be found except for those exiting the NTSC
video encoder and the audio DAC (Digital to Analog Converter).
The downlink signal from the satellite is downconverted from 12.7 - 12.2 GHz to 950
- 1450 MHz by the LNB (Low Noise Block) converter. The tuner then isolates a single
digitally modulated 24 MHz transponder. The demodulator converts the modulated
data to a digital data stream.
The data is encoded at the transmitter site by a process that enables the decoder to
reassemble the data and verify and correct errors that may have occurred during
transmission. This process is called Forward ErrorCorrection (FEe). The error
corrected data is output to the transport IC via an 8-bit parallel interface.
The transport IC is the heart of the receiver data processing circuitry. Data from the
FEC block is processed by the transport IC and sent to respective audio and video
decoders. The microprocessor communicates with the audio and video decoders
through the transport IC. The access card interface is also processed through the
transport IC.
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Figure 8, Receiver Block Diagram