User's Manual

Pulse width of spikes which must be
suppressed by the input filter
tSP 0 50 ns
S_SCL clock frequency fSCL 0 400 kHz
LOW period of the S_SCL clock tLOW 1.3 – sˢ
HIGH period of the S_SCL clock tHIGH 0.6 – sˢ
Data hold time tHD;DAT 100 – ns
Data set-up time tSU;DAT 100 – ns
Figure 6: Definition of Timing for F/S-Mode Devices on the I
2
C-Bus